clk_timesim.v

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: H.42
//  \   \         Application: netgen
//  /   /         Filename: clk_timesim.v
// /___/   /\     Timestamp: Wed Jan 09 17:20:10 2008
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -s 4 -pcf clk.pcf -sdf_anno true -w -ofmt verilog -sim clk.ncd clk_timesim.v 
// Device	: 3s400pq208-4 (PRODUCTION 1.37 2005-07-22)
// Input file	: clk.ncd
// Output file	: clk_timesim.v
// # of Modules	: 1
// Design Name	: clk
// Xilinx	: D:/Xilinx
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Verification Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module clk (
  clk, rst, clk1
);
  input clk;
  input rst;
  output clk1;
  wire \clk_BUFGP/IBUFG ;
  wire clk1_OBUF;
  wire GLOBAL_LOGIC1;
  wire clk_BUFGP;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \clk/INBUF ;
  wire \clk1/ENABLE ;
  wire \clk1/O ;
  wire \rst/INBUF ;
  wire \clk_BUFGP/BUFG/S_INVNOT ;
  wire \clk1_OBUF/DYMUX ;
  wire \clk1_OBUF/SRINVNOT ;
  wire \clk1_OBUF/CLKINV ;
  wire GND;
  wire VCC;
  initial $sdf_annotate("clk_timesim.sdf");
  X_IPAD \clk/PAD  (
    .PAD(clk)
  );
  X_BUF \clk_BUFGP/IBUFG_0  (
    .I(clk),
    .O(\clk/INBUF )
  );
  X_BUF \clk/IFF/IMUX  (
    .I(\clk/INBUF ),
    .O(\clk_BUFGP/IBUFG )
  );
  X_OPAD \clk1/PAD  (
    .PAD(clk1)
  );
  X_TRI clk1_OBUF_1 (
    .I(\clk1/O ),
    .CTL(\clk1/ENABLE ),
    .O(clk1)
  );
  X_INV \clk1/ENABLEINV  (
    .I(GTS),
    .O(\clk1/ENABLE )
  );
  X_IPAD \rst/PAD  (
    .PAD(rst)
  );
  X_BUF rst_IBUF (
    .I(rst),
    .O(\rst/INBUF )
  );
  X_BUFGMUX \clk_BUFGP/BUFG  (
    .I0(\clk_BUFGP/IBUFG ),
    .I1(GND),
    .S(\clk_BUFGP/BUFG/S_INVNOT ),
    .O(clk_BUFGP),
    .GSR(GSR)
  );
  X_INV \clk_BUFGP/BUFG/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\clk_BUFGP/BUFG/S_INVNOT )
  );
  X_INV \clk1_OBUF/DYMUX_2  (
    .I(clk1_OBUF),
    .O(\clk1_OBUF/DYMUX )
  );
  X_INV \clk1_OBUF/SRINV  (
    .I(\rst/INBUF ),
    .O(\clk1_OBUF/SRINVNOT )
  );
  X_BUF \clk1_OBUF/CLKINV_3  (
    .I(clk_BUFGP),
    .O(\clk1_OBUF/CLKINV )
  );
  defparam clk1_4.INIT = 1'b1;
  X_SFF clk1_4 (
    .I(\clk1_OBUF/DYMUX ),
    .CE(VCC),
    .CLK(\clk1_OBUF/CLKINV ),
    .SET(GSR),
    .RST(GND),
    .SSET(\clk1_OBUF/SRINVNOT ),
    .SRST(GND),
    .O(clk1_OBUF)
  );
  X_ONE GLOBAL_LOGIC1_VCC (
    .O(GLOBAL_LOGIC1)
  );
  X_BUF \clk1/OUTPUT/OFF/OMUX  (
    .I(clk1_OBUF),
    .O(\clk1/O )
  );
  X_ZERO NlwBlock_clk_GND (
    .O(GND)
  );
  X_ONE NlwBlock_clk_VCC (
    .O(VCC)
  );
endmodule