clk.par

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

Release 7.1.04i par H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

SOFT-A30872027C::  Wed Jan 09 17:20:02 2008

par -w -intstyle ise -ol std -t 1 clk_map.ncd clk.ncd clk.pcf 


Constraints file: clk.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "clk" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.37 2005-07-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs             3 out of 141     2%
      Number of LOCed IOBs             0 out of 3       0%

   Number of Slices                    1 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98968e) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.8
.
Phase 6.8 (Checksum:989a03) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs 

Writing design to file clk.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 6 unrouted;       REAL time: 1 secs 

Phase 2: 4 unrouted;       REAL time: 2 secs 

Phase 3: 0 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 


Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX6| No   |    1 |  0.000     |  1.033      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  76 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file clk.ncd



PAR done!