vsp2232.syr

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

 0011  | 00010
 0100  | 00001
-------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <FSM_2> on signal <t3[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 00
 0001  | 01
 0010  | 11
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <t2[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <t1[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 5
# Adders/Subtractors               : 5
 15-bit adder                      : 2
 4-bit adder                       : 3
# Registers                        : 22
 1-bit register                    : 17
 15-bit register                   : 2
 4-bit register                    : 3
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <VSP2232> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block VSP2232, actual ratio is 2.
FlipFlop t4_FFd4 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : VSP2232.ngr
Top Level Output File Name         : VSP2232
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 8

Macro Statistics :
# Registers                        : 11
#      1-bit register              : 6
#      15-bit register             : 2
#      4-bit register              : 3
# Multiplexers                     : 1
#      4-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 2
#      15-bit adder                : 2

Cell Usage :
# BELS                             : 254
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 2
#      LUT1_L                      : 26
#      LUT2                        : 30
#      LUT2_D                      : 1
#      LUT2_L                      : 21
#      LUT3                        : 11
#      LUT3_D                      : 2
#      LUT3_L                      : 3
#      LUT4                        : 43
#      LUT4_D                      : 9
#      LUT4_L                      : 41
#      MUXCY                       : 28
#      MUXF5                       : 3
#      VCC                         : 1
#      XORCY                       : 28
# FlipFlops/Latches                : 60
#      FDR                         : 50
#      FDRE                        : 1
#      FDRS                        : 4
#      FDS                         : 4
#      FDSE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 7
#      IBUF                        : 1
#      OBUF                        : 6
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     104  out of   3584     2%  
 Number of Slice Flip Flops:            60  out of   7168     0%  
 Number of 4 input LUTs:               189  out of   7168     2%  
 Number of bonded IOBs:                  8  out of    141     5%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 60    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 9.022ns (Maximum Frequency: 110.840MHz)
   Minimum input arrival time before clock: 5.283ns
   Maximum output required time after clock: 7.271ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 9.022ns (frequency: 110.840MHz)
  Total number of paths / destination ports: 2860 / 64
-------------------------------------------------------------------------
Delay:               9.022ns (Levels of Logic = 5)
  Source:            ve_6 (FF)
  Destination:       ve_14 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: ve_6 to ve_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              4   0.720   1.256  ve_6 (ve_6)
     LUT4:I0->O            2   0.551   0.945  Ker15_SW1 (N150)
     LUT4:I2->O            3   0.551   0.933  Ker18 (N18)
     LUT4:I3->O            1   0.551   0.827  Ker1_SW1 (N68)
     LUT4:I3->O           15   0.551   1.383  Ker1 (N12)
     LUT2_L:I1->LO         1   0.551   0.000  _n0037<13>1 (_n0037<13>)
     FDR:D                     0.203          ve_13
    ----------------------------------------
    Total                      9.022ns (3.678ns logic, 5.344ns route)
                                       (40.8% logic, 59.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 60 / 60
-------------------------------------------------------------------------
Offset:              5.283ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       t3_FFd2 (FF)
  Destination Clock: clk rising

  Data Path: rst to t3_FFd2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   0.877  rst_IBUF (rst_IBUF)
     INV:I->O             59   0.551   2.008  t1_FFd1_N01_INV_0 (t1_FFd1_N0)
     FDRS:R                    1.026          t1_FFd1
    ----------------------------------------
    Total                      5.283ns (2.398ns logic, 2.885ns route)
                                       (45.4% logic, 54.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset:              7.271ns (Levels of Logic = 1)
  Source:            pblk (FF)
  Destination:       pblk (PAD)
  Source Clock:      clk rising

  Data Path: pblk to pblk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              3   0.720   0.907  pblk (pblk_OBUF)
     OBUF:I->O                 5.644          pblk_OBUF (pblk)
    ----------------------------------------
    Total                      7.271ns (6.364ns logic, 0.907ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================
CPU : 9.05 / 9.58 s | Elapsed : 9.00 / 9.00 s
 
--> 

Total memory usage is 102680 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)