icx229.twr

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise d:\test\icx229al\ICX229AL.ise -intstyle ise -e 3
-l 3 -s 4 -xml ICX229 ICX229.ncd -o ICX229.twr ICX229.pcf


Design file:              icx229.ncd
Physical constraint file: icx229.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.37 2005-07-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
rst         |    4.115(R)|   -0.353(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
h1          |    9.486(R)|clk_BUFGP         |   0.000|
h2          |    9.228(R)|clk_BUFGP         |   0.000|
r           |    7.382(R)|clk_BUFGP         |   0.000|
sub         |    9.700(R)|clk_BUFGP         |   0.000|
v1          |    9.392(R)|clk_BUFGP         |   0.000|
v1h         |    9.962(R)|clk_BUFGP         |   0.000|
v2          |    9.098(R)|clk_BUFGP         |   0.000|
v3          |    9.589(R)|clk_BUFGP         |   0.000|
v3h         |    9.915(R)|clk_BUFGP         |   0.000|
v4          |    9.307(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   12.765|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sat Jan 19 16:44:43 2008
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Peak Memory Usage: 93 MB