serial_timesim.v

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: H.42
//  \   \         Application: netgen
//  /   /         Filename: serial_timesim.v
// /___/   /\     Timestamp: Fri Jan 11 17:04:52 2008
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -s 4 -pcf serial.pcf -sdf_anno true -w -ofmt verilog -sim serial.ncd serial_timesim.v 
// Device	: 3s400pq208-4 (PRODUCTION 1.37 2005-07-22)
// Input file	: serial.ncd
// Output file	: serial_timesim.v
// # of Modules	: 1
// Design Name	: serial
// Xilinx	: D:/Xilinx
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Verification Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module serial (
  clk, rst, reset, sload, sclk
);
  input clk;
  input rst;
  output reset;
  output sload;
  output sclk;
  wire GLOBAL_LOGIC0;
  wire \sd<0> ;
  wire \sd<1> ;
  wire \_n0026<1> ;
  wire \serial__n0026<1>_cyo ;
  wire \sd<2> ;
  wire \sd<3> ;
  wire \_n0026<2> ;
  wire \_n0026<3> ;
  wire \serial__n0026<3>_cyo ;
  wire \sd<4> ;
  wire \sd<5> ;
  wire \_n0026<4> ;
  wire \_n0026<5> ;
  wire \sd<6> ;
  wire \sd<7> ;
  wire \_n0026<6> ;
  wire \_n0026<7> ;
  wire _n0037_0;
  wire clk_BUFGP;
  wire rst_IBUF;
  wire \sa<0> ;
  wire \sa<1> ;
  wire \serial_sa__n0000<1>_cyo ;
  wire \sa<2> ;
  wire \sa<3> ;
  wire \serial_sa__n0000<3>_cyo ;
  wire \sa<4> ;
  wire \sa<5> ;
  wire \sa<6> ;
  wire \sa<7> ;
  wire _n0038_0;
  wire \sc<0> ;
  wire \sc<1> ;
  wire \serial_sc__n0000<1>_cyo ;
  wire \sc<2> ;
  wire \sc<3> ;
  wire \serial_sc__n0000<3>_cyo ;
  wire \sc<4> ;
  wire \sc<5> ;
  wire \sc<6> ;
  wire \sc<7> ;
  wire \sb<0> ;
  wire \sb<1> ;
  wire \_n0025<1> ;
  wire \serial__n0025<1>_cyo ;
  wire \sb<2> ;
  wire \sb<3> ;
  wire \_n0025<2> ;
  wire \_n0025<3> ;
  wire \serial__n0025<3>_cyo ;
  wire \sb<4> ;
  wire \sb<5> ;
  wire \_n0025<4> ;
  wire \_n0025<5> ;
  wire \sb<6> ;
  wire \sb<7> ;
  wire \_n0025<6> ;
  wire \_n0025<7> ;
  wire sload_OBUF;
  wire \clk_BUFGP/IBUFG ;
  wire sclk_OBUF;
  wire s1_FFd1;
  wire _n0000;
  wire GLOBAL_LOGIC1;
  wire _n0008_0;
  wire s3_FFd1;
  wire \s4_FFd1-In_0 ;
  wire _n0012;
  wire \s2_FFd1-In_0 ;
  wire s4_FFd1;
  wire CHOICE3_0;
  wire CHOICE11_0;
  wire \_n00381_SW0/O ;
  wire N91_0;
  wire s2_FFd1;
  wire N224;
  wire N81_0;
  wire s5_FFd1;
  wire N197_0;
  wire \Ker011_SW1/O ;
  wire CHOICE58_0;
  wire \s4_FFd1-In1_SW0/O ;
  wire CHOICE34_0;
  wire N28;
  wire \Ker8_SW1/O ;
  wire N111_0;
  wire N220_0;
  wire N4_0;
  wire N01;
  wire CHOICE63_0;
  wire \s3_FFd1-In_0 ;
  wire \_n00141/O ;
  wire N240_0;
  wire CHOICE17_0;
  wire CHOICE25;
  wire \Ker9_SW0/O ;
  wire N206_0;
  wire \_n0021<0>18_SW0_SW3/O ;
  wire N215_0;
  wire \s2_FFd1-In1_SW1/O ;
  wire N199_0;
  wire \s3_FFd1-In1_SW0/O ;
  wire CHOICE28_0;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \_n0026<1>/LOGIC_ONE ;
  wire \_n0026<1>/CYINIT ;
  wire \_n0026<1>/CYSELF ;
  wire N7;
  wire \_n0026<1>/XORG ;
  wire \_n0026<1>/CYMUXG ;
  wire \serial__n0026<0>_cyo ;
  wire \_n0026<1>/LOGIC_ZERO ;
  wire \_n0026<1>/CYSELG ;
  wire \_n0026<1>/G ;
  wire \_n0026<2>/XORF ;
  wire \_n0026<2>/CYINIT ;
  wire \_n0026<2>/F ;
  wire \_n0026<2>/XORG ;
  wire \serial__n0026<2>_cyo ;
  wire \_n0026<2>/CYSELF ;
  wire \_n0026<2>/CYMUXFAST ;
  wire \_n0026<2>/CYAND ;
  wire \_n0026<2>/FASTCARRY ;
  wire \_n0026<2>/CYMUXG2 ;
  wire \_n0026<2>/CYMUXF2 ;
  wire \_n0026<2>/LOGIC_ZERO ;
  wire \_n0026<2>/CYSELG ;
  wire \_n0026<2>/G ;
  wire \_n0026<4>/XORF ;
  wire \_n0026<4>/CYINIT ;
  wire \_n0026<4>/F ;
  wire \_n0026<4>/XORG ;
  wire \serial__n0026<4>_cyo ;
  wire \_n0026<4>/CYSELF ;
  wire \_n0026<4>/CYMUXFAST ;
  wire \_n0026<4>/CYAND ;
  wire \_n0026<4>/FASTCARRY ;
  wire \_n0026<4>/CYMUXG2 ;
  wire \_n0026<4>/CYMUXF2 ;
  wire \_n0026<4>/LOGIC_ZERO ;
  wire \_n0026<4>/CYSELG ;
  wire \_n0026<4>/G ;
  wire \_n0026<6>/XORF ;
  wire \_n0026<6>/LOGIC_ZERO ;
  wire \_n0026<6>/CYINIT ;
  wire \_n0026<6>/CYSELF ;
  wire \_n0026<6>/F ;
  wire \_n0026<6>/XORG ;
  wire \serial__n0026<6>_cyo ;
  wire \sd<7>_rt ;
  wire \sa<0>/DXMUX ;
  wire \sa<0>/LOGIC_ONE ;
  wire \sa<0>/CYINIT ;
  wire \sa<0>/CYSELF ;
  wire N9;
  wire \sa<0>/DYMUX ;
  wire \sa<0>/XORG ;
  wire \sa<0>/CYMUXG ;
  wire \serial_sa__n0000<0>_cyo ;
  wire \sa<0>/LOGIC_ZERO ;
  wire \sa<0>/CYSELG ;
  wire \sa<0>/G ;
  wire \sa<0>/SRINVNOT ;
  wire \sa<0>/CLKINV ;
  wire \sa<0>/CEINV ;
  wire \sa<2>/DXMUX ;
  wire \sa<2>/XORF ;
  wire \sa<2>/CYINIT ;
  wire \sa<2>/F ;
  wire \sa<2>/DYMUX ;
  wire \sa<2>/XORG ;
  wire \serial_sa__n0000<2>_cyo ;
  wire \sa<2>/CYSELF ;
  wire \sa<2>/CYMUXFAST ;
  wire \sa<2>/CYAND ;
  wire \sa<2>/FASTCARRY ;
  wire \sa<2>/CYMUXG2 ;
  wire \sa<2>/CYMUXF2 ;
  wire \sa<2>/LOGIC_ZERO ;
  wire \sa<2>/CYSELG ;
  wire \sa<2>/G ;
  wire \sa<2>/SRINVNOT ;
  wire \sa<2>/CLKINV ;
  wire \sa<2>/CEINV ;
  wire \sa<4>/DXMUX ;
  wire \sa<4>/XORF ;
  wire \sa<4>/CYINIT ;
  wire \sa<4>/F ;
  wire \sa<4>/DYMUX ;
  wire \sa<4>/XORG ;
  wire \serial_sa__n0000<4>_cyo ;
  wire \sa<4>/CYSELF ;
  wire \sa<4>/CYMUXFAST ;
  wire \sa<4>/CYAND ;
  wire \sa<4>/FASTCARRY ;
  wire \sa<4>/CYMUXG2 ;
  wire \sa<4>/CYMUXF2 ;
  wire \sa<4>/LOGIC_ZERO ;
  wire \sa<4>/CYSELG ;
  wire \sa<4>/G ;
  wire \sa<4>/SRINVNOT ;
  wire \sa<4>/CLKINV ;
  wire \sa<4>/CEINV ;
  wire \sa<6>/DXMUX ;
  wire \sa<6>/XORF ;
  wire \sa<6>/LOGIC_ZERO ;
  wire \sa<6>/CYINIT ;
  wire \sa<6>/CYSELF ;
  wire \sa<6>/F ;
  wire \sa<6>/DYMUX ;
  wire \sa<6>/XORG ;
  wire \serial_sa__n0000<6>_cyo ;
  wire \sa<7>_rt ;
  wire \sa<6>/SRINVNOT ;
  wire \sa<6>/CLKINV ;
  wire \sa<6>/CEINV ;
  wire \sc<0>/DXMUX ;
  wire \sc<0>/LOGIC_ONE ;
  wire \sc<0>/CYINIT ;
  wire \sc<0>/CYSELF ;
  wire N8;
  wire \sc<0>/DYMUX ;
  wire \sc<0>/XORG ;
  wire \sc<0>/CYMUXG ;
  wire \serial_sc__n0000<0>_cyo ;
  wire \sc<0>/LOGIC_ZERO ;
  wire \sc<0>/CYSELG ;
  wire \sc<0>/G ;
  wire \sc<0>/SRINVNOT ;
  wire \sc<0>/CLKINV ;
  wire \sc<0>/CEINV ;
  wire \sd<5>/DXMUX ;
  wire \_n0024<5>1/O ;
  wire \sd<5>/DYMUX ;
  wire \_n0024<4>1/O ;
  wire \sd<5>/SRINVNOT ;
  wire \sd<5>/CLKINV ;
  wire _n0008;
  wire CHOICE25_pack_1;
  wire \sd<6>/DYMUX ;
  wire \_n0024<6>1/O ;
  wire \sd<6>/SRINVNOT ;
  wire \sd<6>/CLKINV ;
  wire N220;
  wire \s5_FFd1/REVUSED ;
  wire \s5_FFd1/DYMUX ;
  wire \s5_FFd1-In11/O ;
  wire \s5_FFd1/SRINVNOT ;
  wire \s5_FFd1/CLKINV ;
  wire N81;
  wire N28_pack_1;
  wire N91;
  wire \Ker9_SW0/O_pack_1 ;
  wire CHOICE44;
  wire \_n0021<0>18_SW0_SW3/O_pack_1 ;
  wire \s2_FFd1/DXMUX ;
  wire \s2_FFd1/FXMUX ;
  wire \s2_FFd1-In ;
  wire \s2_FFd1-In1_SW1/O_pack_1 ;
  wire \s2_FFd1/SRINVNOT ;
  wire \s2_FFd1/CLKINV ;
  wire \s2_FFd1/CEINV ;
  wire \s3_FFd1-In ;
  wire \s3_FFd1-In1_SW0/O_pack_1 ;
  wire N4;
  wire _n0012_pack_1;
  wire CHOICE17;
  wire N240;
  wire CHOICE11;
  wire N206;
  wire CHOICE63;
  wire \s1_FFd1/DXMUX ;
  wire \s1_FFd1/REVUSED ;
  wire \s1_FFd1/SRINVNOT ;
  wire \s1_FFd1/CLKINV ;
  wire N197;
  wire CHOICE34;
  wire N215;
  wire N199;
  wire CHOICE3;
  wire \s3_FFd1/DYMUX ;
  wire \s3_FFd1/SRINVNOT ;
  wire \s3_FFd1/CLKINV ;
  wire \s3_FFd1/CEINV ;
  wire CHOICE28;
  wire \rst/INBUF ;
  wire \reset/ENABLE ;
  wire \reset/O ;
  wire \clk_BUFGP/BUFG/S_INVNOT ;
  wire \sload_OBUF/DXMUX ;
  wire \sload_OBUF/F5MUX ;
  wire \_n00201_G/O ;
  wire \sload_OBUF/BXINV ;
  wire \_n00201_F/O ;
  wire \sload_OBUF/SRINVNOT ;
  wire \sload_OBUF/CLKINV ;
  wire _n0037;
  wire _n0000_pack_1;
  wire _n0038;
  wire \_n00381_SW0/O_pack_1 ;
  wire \sd<1>/DXMUX ;
  wire \_n0024<1>1/O ;
  wire N224_pack_1;
  wire \sd<1>/SRINVNOT ;
  wire \sd<1>/CLKINV ;
  wire CHOICE58;
  wire \Ker011_SW1/O_pack_1 ;
  wire \s4_FFd1/DXMUX ;
  wire \s4_FFd1/FXMUX ;
  wire \s4_FFd1-In ;
  wire \s4_FFd1-In1_SW0/O_pack_1 ;
  wire \s4_FFd1/SRINVNOT ;
  wire \s4_FFd1/CLKINV ;
  wire \s4_FFd1/CEINV ;
  wire N111;
  wire \Ker8_SW1/O_pack_1 ;
  wire \sd<0>/DXMUX ;
  wire \_n0024<0>/O ;
  wire \sd<0>/DYMUX ;
  wire \_n00231/O ;
  wire \sd<0>/SRINVNOT ;
  wire \sd<0>/CLKINV ;
  wire _n0036;
  wire \sb<0>/REVUSED ;
  wire \sb<0>/DYMUX ;
  wire \_n0021<0>471/O ;
  wire \sb<0>/SRINVNOT ;
  wire \sb<0>/CLKINV ;
  wire \sb<1>/DXMUX ;
  wire \_n0021<1>1/O ;
  wire N01_pack_1;
  wire \sb<1>/SRINVNOT ;
  wire \sb<1>/CLKINV ;
  wire \sd<7>/DXMUX ;
  wire \_n0024<7>1/O ;
  wire \_n00141/O_pack_1 ;
  wire \sd<7>/SRINVNOT ;
  wire \sd<7>/CLKINV ;
  wire \sb<3>/DXMUX ;
  wire \_n0021<3>1/O ;
  wire \sb<3>/DYMUX ;
  wire \_n0021<2>1/O ;
  wire \sb<3>/SRINVNOT ;
  wire \sb<3>/CLKINV ;
  wire \sb<5>/DXMUX ;
  wire \_n0021<5>1/O ;
  wire \sb<5>/DYMUX ;
  wire \_n0021<4>1/O ;
  wire \sb<5>/SRINVNOT ;
  wire \sb<5>/CLKINV ;
  wire \sb<7>/DXMUX ;
  wire \_n0021<7>1/O ;
  wire \sb<7>/DYMUX ;
  wire \_n0021<6>1/O ;
  wire \sb<7>/SRINVNOT ;
  wire \sb<7>/CLKINV ;
  wire \sd<3>/DXMUX ;
  wire \_n0024<3>1/O ;
  wire \sd<3>/DYMUX ;
  wire \_n0024<2>1/O ;
  wire \sd<3>/SRINVNOT ;
  wire \sd<3>/CLKINV ;
  wire \sc<2>/DXMUX ;
  wire \sc<2>/XORF ;
  wire \sc<2>/CYINIT ;
  wire \sc<2>/F ;
  wire \sc<2>/DYMUX ;
  wire \sc<2>/XORG ;
  wire \serial_sc__n0000<2>_cyo ;
  wire \sc<2>/CYSELF ;
  wire \sc<2>/CYMUXFAST ;
  wire \sc<2>/CYAND ;
  wire \sc<2>/FASTCARRY ;
  wire \sc<2>/CYMUXG2 ;
  wire \sc<2>/CYMUXF2 ;
  wire \sc<2>/LOGIC_ZERO ;
  wire \sc<2>/CYSELG ;
  wire \sc<2>/G ;
  wire \sc<2>/SRINVNOT ;
  wire \sc<2>/CLKINV ;
  wire \sc<2>/CEINV ;
  wire \sc<4>/DXMUX ;
  wire \sc<4>/XORF ;
  wire \sc<4>/CYINIT ;
  wire \sc<4>/F ;
  wire \sc<4>/DYMUX ;
  wire \sc<4>/XORG ;
  wire \serial_sc__n0000<4>_cyo ;
  wire \sc<4>/CYSELF ;
  wire \sc<4>/CYMUXFAST ;
  wire \sc<4>/CYAND ;
  wire \sc<4>/FASTCARRY ;
  wire \sc<4>/CYMUXG2 ;
  wire \sc<4>/CYMUXF2 ;
  wire \sc<4>/LOGIC_ZERO ;
  wire \sc<4>/CYSELG ;
  wire \sc<4>/G ;
  wire \sc<4>/SRINVNOT ;
  wire \sc<4>/CLKINV ;
  wire \sc<4>/CEINV ;
  wire \sc<6>/DXMUX ;
  wire \sc<6>/XORF ;
  wire \sc<6>/LOGIC_ZERO ;
  wire \sc<6>/CYINIT ;
  wire \sc<6>/CYSELF ;
  wire \sc<6>/F ;
  wire \sc<6>/DYMUX ;
  wire \sc<6>/XORG ;
  wire \serial_sc__n0000<6>_cyo ;
  wire \sc<7>_rt ;
  wire \sc<6>/SRINVNOT ;
  wire \sc<6>/CLKINV ;
  wire \sc<6>/CEINV ;
  wire \_n0025<1>/LOGIC_ONE ;
  wire \_n0025<1>/CYINIT ;
  wire \_n0025<1>/CYSELF ;
  wire N6;
  wire \_n0025<1>/XORG ;
  wire \_n0025<1>/CYMUXG ;
  wire \serial__n0025<0>_cyo ;
  wire \_n0025<1>/LOGIC_ZERO ;
  wire \_n0025<1>/CYSELG ;
  wire \_n0025<1>/G ;
  wire \_n0025<2>/XORF ;
  wire \_n0025<2>/CYINIT ;
  wire \_n0025<2>/F ;
  wire \_n0025<2>/XORG ;
  wire \serial__n0025<2>_cyo ;
  wire \_n0025<2>/CYSELF ;
  wire \_n0025<2>/CYMUXFAST ;
  wire \_n0025<2>/CYAND ;
  wire \_n0025<2>/FASTCARRY ;
  wire \_n0025<2>/CYMUXG2 ;
  wire \_n0025<2>/CYMUXF2 ;
  wire \_n0025<2>/LOGIC_ZERO ;
  wire \_n0025<2>/CYSELG ;
  wire \_n0025<2>/G ;
  wire \_n0025<4>/XORF ;
  wire \_n0025<4>/CYINIT ;
  wire \_n0025<4>/F ;
  wire \_n0025<4>/XORG ;
  wire \serial__n0025<4>_cyo ;
  wire \_n0025<4>/CYSELF ;
  wire \_n0025<4>/CYMUXFAST ;
  wire \_n0025<4>/CYAND ;
  wire \_n0025<4>/FASTCARRY ;
  wire \_n0025<4>/CYMUXG2 ;
  wire \_n0025<4>/CYMUXF2 ;
  wire \_n0025<4>/LOGIC_ZERO ;
  wire \_n0025<4>/CYSELG ;
  wire \_n0025<4>/G ;
  wire \_n0025<6>/XORF ;
  wire \_n0025<6>/LOGIC_ZERO ;
  wire \_n0025<6>/CYINIT ;
  wire \_n0025<6>/CYSELF ;
  wire \_n0025<6>/F ;
  wire \_n0025<6>/XORG ;
  wire \serial__n0025<6>_cyo ;
  wire \sb<7>_rt ;
  wire \sload/ENABLE ;
  wire \sload/O ;
  wire \clk/INBUF ;
  wire \sclk/ENABLE ;
  wire \sclk/O ;
  wire \reset/OUTPUT/OTCLK1INV ;
  wire reset_OBUF;
  wire \reset/OUTPUT/OFF/OREV_USED ;
  wire \reset/OUTPUT/OFF/OSR_USED ;
  wire \reset/OUTPUT/OFF/OCEINV ;
  wire \reset/OUTPUT/OFF/O1INV ;
  wire VCC;
  wire GND;
  initial $sdf_annotate("serial_timesim.sdf");
  X_ZERO \_n0026<1>/LOGIC_ZERO_0  (
    .O(\_n0026<1>/LOGIC_ZERO )
  );
  X_ONE \_n0026<1>/LOGIC_ONE_1  (
    .O(\_n0026<1>/LOGIC_ONE )
  );
  X_MUX2 \_n0026<1>/CYMUXF  (
    .IA(\_n0026<1>/LOGIC_ONE ),
    .IB(\_n0026<1>/CYINIT ),
    .SEL(\_n0026<1>/CYSELF ),
    .O(\serial__n0026<0>_cyo )
  );
  X_BUF \_n0026<1>/CYINIT_2  (
    .I(GLOBAL_LOGIC0),
    .O(\_n0026<1>/CYINIT )
  );
  X_BUF \_n0026<1>/CYSELF_3  (
    .I(N7),
    .O(\_n0026<1>/CYSELF )
  );
  X_BUF \_n0026<1>/YUSED  (
    .I(\_n0026<1>/XORG ),
    .O(\_n0026<1> )
  );
  X_XOR2 \_n0026<1>/XORG_4  (
    .I0(\serial__n0026<0>_cyo ),
    .I1(\_n0026<1>/G ),
    .O(\_n0026<1>/XORG )
  );
  X_BUF \_n0026<1>/COUTUSED  (
    .I(\_n0026<1>/CYMUXG ),
    .O(\serial__n0026<1>_cyo )
  );
  X_MUX2 \_n0026<1>/CYMUXG_5  (
    .IA(\_n0026<1>/LOGIC_ZERO ),
    .IB(\serial__n0026<0>_cyo ),
    .SEL(\_n0026<1>/CYSELG ),
    .O(\_n0026<1>/CYMUXG )
  );
  X_BUF \_n0026<1>/CYSELG_6  (
    .I(\_n0026<1>/G ),
    .O(\_n0026<1>/CYSELG )
  );
  X_ZERO \_n0026<2>/LOGIC_ZERO_7  (
    .O(\_n0026<2>/LOGIC_ZERO )
  );
  X_BUF \_n0026<2>/XUSED  (
    .I(\_n0026<2>/XORF ),
    .O(\_n0026<2> )
  );
  X_XOR2 \_n0026<2>/XORF_8  (
    .I0(\_n0026<2>/CYINIT ),
    .I1(\_n0026<2>/F ),
    .O(\_n0026<2>/XORF )
  );
  X_MUX2 \_n0026<2>/CYMUXF  (
    .IA(\_n0026<2>/LOGIC_ZERO ),
    .IB(\_n0026<2>/CYINIT ),
    .SEL(\_n0026<2>/CYSELF ),
    .O(\serial__n0026<2>_cyo )
  );
  X_MUX2 \_n0026<2>/CYMUXF2_9  (
    .IA(\_n0026<2>/LOGIC_ZERO ),
    .IB(\_n0026<2>/LOGIC_ZERO ),
    .SEL(\_n0026<2>/CYSELF ),
    .O(\_n0026<2>/CYMUXF2 )
  );
  X_BUF \_n0026<2>/CYINIT_10  (
    .I(\serial__n0026<1>_cyo ),
    .O(\_n0026<2>/CYINIT )
  );
  X_BUF \_n0026<2>/CYSELF_11  (
    .I(\_n0026<2>/F ),
    .O(\_n0026<2>/CYSELF )
  );
  X_BUF \_n0026<2>/YUSED  (
    .I(\_n0026<2>/XORG ),
    .O(\_n0026<3> )
  );
  X_XOR2 \_n0026<2>/XORG_12  (
    .I0(\serial__n0026<2>_cyo ),
    .I1(\_n0026<2>/G ),
    .O(\_n0026<2>/XORG )
  );
  X_BUF \_n0026<2>/COUTUSED  (
    .I(\_n0026<2>/CYMUXFAST ),
    .O(\serial__n0026<3>_cyo )
  );
  X_BUF \_n0026<2>/FASTCARRY_13  (
    .I(\serial__n0026<1>_cyo ),
    .O(\_n0026<2>/FASTCARRY )
  );
  X_AND2 \_n0026<2>/CYAND_14  (
    .I0(\_n0026<2>/CYSELG ),
    .I1(\_n0026<2>/CYSELF ),
    .O(\_n0026<2>/CYAND )