📄 top.mrp
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Release 7.1.04i Map H.42Xilinx Mapping Report File for Design 'top'Design Information------------------Command Line : D:/Xilinx/bin/nt/map.exe -ise d:\test\icx229al\ICX229AL.ise
-intstyle ise -p xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -o top_map.ncd
top.ngd top.pcf Target Device : xc3s400Target Package : pq208Target Speed : -4Mapper Version : spartan3 -- $Revision: 1.26.6.4 $Mapped Date : Sat Jan 19 16:49:01 2008Design Summary--------------Number of errors: 0Number of warnings: 2Logic Utilization: Number of Slice Flip Flops: 433 out of 7,168 6% Number of 4 input LUTs: 1,157 out of 7,168 16%Logic Distribution: Number of occupied Slices: 773 out of 3,584 21% Number of Slices containing only related logic: 773 out of 773 100% Number of Slices containing unrelated logic: 0 out of 773 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 1,444 out of 7,168 20% Number used as logic: 1,157 Number used as a route-thru: 287 Number of bonded IOBs: 23 out of 141 16% IOB Flip Flops: 4 Number of GCLKs: 3 out of 8 37% Number of DCMs: 1 out of 4 25%Total equivalent gate count for design: 19,205Additional JTAG gate count for IOBs: 1,104Peak Memory Usage: 121 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_XLXI_2/sclk/XLXI_2/sclk_BUFG" (output
signal=XLXI_2/sclk) has a mix of clock and non-clock loads. The non-clock
loads are: Pin I0 of XLXI_2/_n00241WARNING:Pack:266 - The function generator XLXI_1/Ker5328 failed to merge with F5
multiplexer XLXI_1/_n0137<0>151. There is a conflict for the FXMUX. The
design will exhibit suboptimal timing.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "XLXI_2/sclk_BUFG" (output signal=XLXI_2/sclk), BUFG symbol "XLXI_8/CLK0_BUFG_INST" (output signal=XLXN_15), BUFG symbol "XLXI_8/CLK2X_BUFG_INST" (output signal=clkbp_OBUF)INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| adcck | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || clk | IOB | INPUT | LVCMOS25 | | | | | || clkbp | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || clpdm | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || clpob | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || h1 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || h2 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pblk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || r | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || reset | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || rst | IOB | INPUT | LVCMOS25 | | | | | || sclk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || sdata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || shd | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || shp | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || sload | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || sub | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || v1 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || v2 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || v3 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || v4 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || v1h | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || v3h | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 23Number of Equivalent Gates for Design = 19,205Number of RPM Macros = 0Number of Hard Macros = 0DCIRESETs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DCMs = 1GCLKs = 3ICAPs = 018X18 Multipliers = 0Block RAMs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 35IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 1IOB Flip Flops = 4Unbonded IOBs = 0Bonded IOBs = 23XORs = 286CARRY_INITs = 160CARRY_SKIPs = 0CARRY_MUXes = 286Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFs = 14MULT_ANDs = 04 input LUTs used as Route-Thrus = 2874 input LUTs = 1157Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 34Slice Flip Flops = 433SliceMs = 0SliceLs = 773Slices = 773F6 Muxes = 0F5 Muxes = 14F8 Muxes = 0F7 Muxes = 0Number of LUT signals with 4 loads = 36Number of LUT signals with 3 loads = 65Number of LUT signals with 2 loads = 94Number of LUT signals with 1 load = 862NGM Average fanout of LUT = 2.06NGM Maximum fanout of LUT = 31NGM Average fanin for LUT = 3.5549Number of LUT symbols = 1157⌨️ 快捷键说明
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