vsp2232.v

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

module VSP2232(clk,rst,clpdm,shp,shd,adcck,clpob,pblk); //clk周期为8.73ns
  input clk,rst;
  output clpdm,shp,shd,adcck,clpob,pblk;
  reg clpdm,shp,shd,adcck,clpob,pblk;
  reg [3:0]va,vb,vc;
  reg [14:0]vd,ve,vf;
  reg [3:0]t1,t2,t3,t4,t5,t6;

  always@(posedge clk)
    if(!rst)
	   begin
	      clpdm<=1;
	 		vf<=0;
			t6<=0;
      end
	 else
	   case(t6)
		     0:if(vf==796)
			      begin
					   clpdm<=0;
						vf<=0;
						t6<=1;
               end
             else
					   vf<=vf+1;
           1:if(vf==175)
			      begin
					   clpdm<=1;
						vf<=0;
						t6<=2;
               end
             else
					vf<=vf+1;
           2:if(vf==7151)
			      begin
					   clpdm<=0;
						vf<=0;
						t6<=1;
               end
             else
					vf<=vf+1;
        endcase

  always@(posedge clk)
	   if(!rst)
		  begin
		     shp<=1;
			  va<=0;
			  t1<=0;					
		  end
		else 
		  case(t1)
           0:if(va==4)
		         begin
			   		shp<=0;
						va<=0;
						t1<=1;
			  		end
          	 else
				   va<=va+1;
		     1:if(va==7)
		         begin
			   		shp<=0;
						va<=0;
						t1<=1;
			  		end
          	 else
			  		begin
			   		shp<=1;
						va<=va+1;
			  		end
		  endcase
	
  always@(posedge clk)
	   if(!rst)
		  begin
		     shd<=1;
			  vb<=0;
			  t2<=0;					
		  end
		else 
		  case(t2)
           0:if(vb==7)
		         begin
			   		shd<=0;
						vb<=0;
						t2<=1;
			  		end
          	 else
               vb<=vb+1;
		     1:if(vb==7)
		         begin
			   		shd<=0;
						vb<=0;
						t2<=1;
			  		end
          	 else
			  		begin
			   		shd<=1;
						vb<=vb+1;
			  		end
		  endcase

  always@(posedge clk)
	   if(!rst)
		  begin
		     adcck<=0;
			  vc<=0;
			  t3<=0;					
		  end
		else 
		  case(t3)
           0:if(vc==3)
		         begin
			   		adcck<=1;
						vc<=0;
						t3<=1;
			  		end
          	 else
					vc<=vc+1;
		     1:if(vc==3)
		         begin
			   		adcck<=0;
						vc<=0;
						t3<=2;
			  		end
          	 else
					vc<=vc+1;
           2:if(vc==3)
		         begin
			   		adcck<=1;
						vc<=0;
						t3<=1;
			  		end
          	 else
				   vc<=vc+1;
		  endcase

  always@(posedge clk)
      if(!rst)
		  begin
		     clpob<=1;
			  vd<=0;
			  t4<=0;
        end
      else
		  case(t4)
		     0:if(vd==972)
			      begin
					   clpob<=0;
						vd<=0;
						t4<=1;
               end
             else
					vd<=vd+1;
           1:if(vd==23)
			      begin
					   clpob<=1;
						vd<=0;
						t4<=2;
               end
             else
					vd<=vd+1;
           2:if(vd==6015)
			      begin
					   clpob<=0;
						vd<=0;
						t4<=3;
               end
             else
					vd<=vd+1;
           3:if(vd==319)
			      begin
					   clpob<=1;
						vd<=0;
						t4<=4;
               end
             else
					vd<=vd+1;
			  4:if(vd==967)
			      begin
					   clpob<=0;
						vd<=0;
						t4<=1;
               end
             else
					vd<=vd+1;
		  endcase

  always@(posedge clk)
		if(!rst)
		  begin
		     pblk<=1;
			  ve<=0;
			  t5<=0;
        end
      else
		  case(t5)
		     0:if(ve==796)
			      begin
					   pblk<=1;
						ve<=0;
						t5<=1;
               end
             else
				   begin
              		pblk<=0;
					   ve<=ve+1;
               end
           1:if(ve==6535)
			      begin
					   pblk<=0;
						ve<=0;
						t5<=2;
               end
             else
					ve<=ve+1;
           2:if(ve==791)
			      begin
					   pblk<=1;
						ve<=0;
						t5<=1;
               end
             else
					ve<=ve+1;
        endcase

endmodule