test1.v

来自「SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序」· Verilog 代码 · 共 62 行

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:28:55 01/08/2008
// Design Name:   VSP2232
// Module Name:   test1.v
// Project Name:  ICX229AL
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VSP2232
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test1_v;

	// Inputs
	reg clk;
	reg rst;

	// Outputs
	wire clpdm;

	// Instantiate the Unit Under Test (UUT)
	VSP2232 uut (
		.clk(clk), 
		.rst(rst), 
		.clpdm(clpdm),
		.shp(shp),
		.shd(shd),
		.adcck(adcck),
		.clpob(clpob),
		.pblk(pblk)
	);
	always #4.365 clk=~clk;
	initial begin
		// Initialize Inputs
	   clk = 0;
		rst = 1;
		#10 rst=0;
		#110 rst=1;

		// Wait 100 ns for global reset to finish
		#100000;
        
		// Add stimulus here

	end
      
endmodule