top.syr

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <zhuangtai[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00000 | 00
 00001 | 01
 00010 | 11
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 27
# Adders/Subtractors               : 22
 15-bit adder                      : 12
 3-bit adder                       : 1
 31-bit adder                      : 3
 4-bit adder                       : 3
 5-bit adder                       : 1
 8-bit adder                       : 2
# Counters                         : 2
 8-bit up counter                  : 2
# Registers                        : 120
 1-bit register                    : 97
 15-bit register                   : 12
 16-bit register                   : 1
 3-bit register                    : 1
 31-bit register                   : 3
 4-bit register                    : 3
 5-bit register                    : 1
 8-bit register                    : 2
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <datain_0> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datain_1> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datain_2> (without init value) has a constant value of 0 in block <shuju>.

Optimizing unit <top> ...

Optimizing unit <shuju> ...

Optimizing unit <VSP2232> ...

Optimizing unit <ICX229> ...

Optimizing unit <serial> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 20.
FlipFlop XLXI_1/state13_FFd1 has been replicated 1 time(s)
FlipFlop XLXI_2/reset has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 23

Macro Statistics :
# Registers                        : 60
#      1-bit register              : 36
#      15-bit register             : 12
#      3-bit register              : 1
#      31-bit register             : 3
#      4-bit register              : 3
#      5-bit register              : 1
#      8-bit register              : 4
# Multiplexers                     : 1
#      4-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 19
#      15-bit adder                : 12
#      31-bit adder                : 3
#      8-bit adder                 : 4

Cell Usage :
# BELS                             : 2036
#      GND                         : 1
#      INV                         : 24
#      LUT1                        : 275
#      LUT1_L                      : 11
#      LUT2                        : 99
#      LUT2_D                      : 8
#      LUT2_L                      : 57
#      LUT3                        : 86
#      LUT3_D                      : 12
#      LUT3_L                      : 32
#      LUT4                        : 368
#      LUT4_D                      : 94
#      LUT4_L                      : 382
#      MUXCY                       : 286
#      MUXF5                       : 14
#      VCC                         : 1
#      XORCY                       : 286
# FlipFlops/Latches                : 437
#      FDR                         : 310
#      FDR_1                       : 14
#      FDRE                        : 44
#      FDRS                        : 40
#      FDRS_1                      : 5
#      FDRSE                       : 2
#      FDRSE_1                     : 1
#      FDS                         : 17
#      FDS_1                       : 1
#      FDSE                        : 3
# Clock Buffers                    : 3
#      BUFG                        : 3
# IO Buffers                       : 23
#      IBUF                        : 1
#      IBUFG                       : 1
#      OBUF                        : 21
# DCMs                             : 1
#      DCM                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     780  out of   3584    21%  
 Number of Slice Flip Flops:           437  out of   7168     6%  
 Number of 4 input LUTs:              1424  out of   7168    19%  
 Number of bonded IOBs:                 23  out of    141    16%  
 Number of GCLKs:                        3  out of      8    37%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | XLXI_8/DCM_INST:CLK2X  | 374   |
XLXI_2/sclk:Q                      | BUFG                   | 21    |
clk                                | XLXI_8/DCM_INST:CLK0   | 42    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 23.784ns (Maximum Frequency: 42.045MHz)
   Minimum input arrival time before clock: 7.322ns
   Maximum output required time after clock: 9.267ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 23.784ns (frequency: 42.045MHz)
  Total number of paths / destination ports: 50979 / 503
-------------------------------------------------------------------------
Delay:               11.892ns (Levels of Logic = 7)
  Source:            XLXI_1/a_10 (FF)
  Destination:       XLXI_1/a_14 (FF)
  Source Clock:      clk rising 2.0X
  Destination Clock: clk rising 2.0X

  Data Path: XLXI_1/a_10 to XLXI_1/a_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              4   0.720   1.256  XLXI_1/a_10 (XLXI_1/a_10)
     LUT3:I0->O            1   0.551   0.827  XLXI_1/Ker226_SW0 (N499)
     LUT4_D:I3->O          2   0.551   0.903  XLXI_1/Ker226 (XLXI_1/N226)
     LUT4_D:I3->O          9   0.551   1.192  XLXI_1/_n003441 (XLXI_1/_n0034)
     LUT4:I2->O            1   0.551   0.869  XLXI_1/Ker8852_SW1_SW1 (N4021)
     LUT4:I2->O            1   0.551   0.869  XLXI_1/Ker8852_SW1 (N3866)
     LUT4:I2->O           13   0.551   1.196  XLXI_1/Ker0 (XLXI_1/N01)
     LUT4_L:I3->LO         1   0.551   0.000  XLXI_1/_n0134<4>1 (XLXI_1/_n0134<4>)
     FDR:D                     0.203          XLXI_1/a_4
    ----------------------------------------
    Total                     11.892ns (4.780ns logic, 7.112ns route)
                                       (40.2% logic, 59.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_2/sclk:Q'
  Clock period: 7.886ns (frequency: 126.807MHz)
  Total number of paths / destination ports: 221 / 27
-------------------------------------------------------------------------
Delay:               7.886ns (Levels of Logic = 4)
  Source:            XLXI_7/count_3 (FF)
  Destination:       XLXI_7/datain_8 (FF)
  Source Clock:      XLXI_2/sclk:Q falling
  Destination Clock: XLXI_2/sclk:Q falling

  Data Path: XLXI_7/count_3 to XLXI_7/datain_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q           10   0.720   1.473  XLXI_7/count_3 (XLXI_7/count_3)
     LUT2:I0->O            1   0.551   0.827  XLXI_7/Ker9_SW0 (N23)
     LUT4:I3->O            9   0.551   1.319  XLXI_7/Ker9 (XLXI_7/N91)
     LUT4:I1->O            1   0.551   1.140  XLXI_7/_n0006<8>_SW0 (N29)
     LUT3:I0->O            1   0.551   0.000  XLXI_7/_n0006<8> (XLXI_7/_n0006<8>)
     FDS_1:D                   0.203          XLXI_7/datain_8
    ----------------------------------------
    Total                      7.886ns (3.127ns logic, 4.759ns route)
                                       (39.7% logic, 60.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 416 / 416
-------------------------------------------------------------------------
Offset:              7.322ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       XLXI_3/adcck (FF)
  Destination Clock: clk rising 2.0X

  Data Path: rst to XLXI_3/adcck
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   0.877  rst_IBUF (rst_IBUF)
     INV:I->O            415   0.551   4.047  XLXI_3/t1_FFd1_N01_INV_0 (XLXI_3/t1_FFd1_N0)
     FDRS:R                    1.026          XLXI_3/t1_FFd1
    ----------------------------------------
    Total                      7.322ns (2.398ns logic, 4.924ns route)
                                       (32.8% logic, 67.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 19 / 19
-------------------------------------------------------------------------
Offset:              9.267ns (Levels of Logic = 2)
  Source:            XLXI_2/sclk (FF)
  Destination:       sclk (PAD)
  Source Clock:      clk rising

  Data Path: XLXI_2/sclk to sclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              1   0.720   0.801  XLXI_2/sclk (XLXI_2/sclk1)
     BUFG:I->O            23   0.401   1.701  XLXI_2/sclk_BUFG (XLXI_2/sclk)
     OBUF:I->O                 5.644          sclk_OBUF (sclk)
    ----------------------------------------
    Total                      9.267ns (6.765ns logic, 2.502ns route)
                                       (73.0% logic, 27.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2/sclk:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              7.241ns (Levels of Logic = 1)
  Source:            XLXI_7/sdata (FF)
  Destination:       sdata (PAD)
  Source Clock:      XLXI_2/sclk:Q falling

  Data Path: XLXI_7/sdata to sdata
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            2   0.720   0.877  XLXI_7/sdata (XLXI_7/sdata)
     OBUF:I->O                 5.644          sdata_OBUF (sdata)
    ----------------------------------------
    Total                      7.241ns (6.364ns logic, 0.877ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================
CPU : 55.41 / 55.95 s | Elapsed : 55.00 / 56.00 s
 
--> 

Total memory usage is 113496 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   17 (   0 filtered)
Number of infos    :    2 (   0 filtered)