📄 top.syr

📁 SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序
💻 SYR
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    Found 1-bit register for signal <v4>.    Found 1-bit register for signal <v1h>.    Found 1-bit register for signal <v3h>.    Found 15-bit adder for signal <$n0152> created at line 68.    Found 3-bit adder for signal <$n0153> created at line 199.    Found 15-bit adder for signal <$n0154> created at line 245.    Found 15-bit adder for signal <$n0155> created at line 245.    Found 15-bit adder for signal <$n0156> created at line 443.    Found 15-bit adder for signal <$n0157> created at line 443.    Found 15-bit adder for signal <$n0158> created at line 566.    Found 15-bit adder for signal <$n0159> created at line 566.    Found 15-bit adder for signal <$n0160> created at line 673.    Found 15-bit adder for signal <$n0161> created at line 673.    Found 31-bit adder for signal <$n0162> created at line 825.    Found 31-bit adder for signal <$n0163> created at line 875.    Found 31-bit adder for signal <$n0164> created at line 925.    Found 15-bit adder for signal <$n0165>.    Found 15-bit register for signal <a>.    Found 15-bit register for signal <b>.    Found 15-bit register for signal <d>.    Found 15-bit register for signal <e>.    Found 15-bit register for signal <g>.    Found 15-bit register for signal <h>.    Found 15-bit register for signal <i>.    Found 15-bit register for signal <j>.    Found 15-bit register for signal <l>.    Found 15-bit register for signal <m>.    Found 31-bit register for signal <o>.    Found 31-bit register for signal <p>.    Found 31-bit register for signal <q>.    Found 3-bit register for signal <s>.    Summary:	inferred  16 Finite State Machine(s).	inferred 256 D-type flip-flop(s).	inferred  14 Adder/Subtractor(s).Unit <ICX229> synthesized.Synthesizing Unit <top>.    Related source file is "top.vf".Unit <top> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_26> for best encoding.Optimizing FSM <FSM_26> on signal <state18[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 10000 001   | 01000 010   | 00100 011   | 00010 100   | 00001-------------------Analyzing FSM <FSM_25> for best encoding.Optimizing FSM <FSM_25> on signal <state17[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 10000 001   | 01000 010   | 00100 011   | 00010 100   | 00001-------------------Analyzing FSM <FSM_24> for best encoding.Optimizing FSM <FSM_24> on signal <state16[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 10000 001   | 01000 010   | 00100 011   | 00010 100   | 00001-------------------Analyzing FSM <FSM_23> for best encoding.Optimizing FSM <FSM_23> on signal <state14[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 10000 001   | 01000 010   | 00100 011   | 00010 100   | 00001-------------------Analyzing FSM <FSM_22> for best encoding.Optimizing FSM <FSM_22> on signal <state13[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000   | 00 001   | 01 010   | 10 011   | 11-------------------Analyzing FSM <FSM_21> for best encoding.Optimizing FSM <FSM_21> on signal <state11[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000   | 00 001   | 01 010   | 10-------------------Analyzing FSM <FSM_20> for best encoding.Optimizing FSM <FSM_20> on signal <state10[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000   | 00 001   | 01 010   | 10-------------------Analyzing FSM <FSM_19> for best encoding.Optimizing FSM <FSM_19> on signal <state8[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000   | 00 001   | 01 010   | 10-------------------Analyzing FSM <FSM_18> for best encoding.Optimizing FSM <FSM_18> on signal <state7[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 10000 001   | 01000 010   | 00100 011   | 00010 100   | 00001-------------------Analyzing FSM <FSM_17> for best encoding.Optimizing FSM <FSM_17> on signal <state5[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 10000 001   | 01000 010   | 00100 011   | 00010 100   | 00001-------------------Analyzing FSM <FSM_16> for best encoding.Optimizing FSM <FSM_16> on signal <state4[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 10000 001   | 01000 010   | 00100 011   | 00010 100   | 00001-------------------Analyzing FSM <FSM_15> for best encoding.Optimizing FSM <FSM_15> on signal <state3[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000   | 00 001   | 01 010   | 10-------------------Analyzing FSM <FSM_14> for best encoding.Optimizing FSM <FSM_14> on signal <state2[1:4]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 1000 001   | 0100 010   | 0010 011   | 0001-------------------Analyzing FSM <FSM_13> for best encoding.Optimizing FSM <FSM_13> on signal <state1[1:3]> with sequential encoding.------------------- State | Encoding------------------- 000   | 000 001   | 001 010   | 010 011   | 011 100   | 100 101   | 101 110   | 110 111   | 111-------------------Analyzing FSM <FSM_12> for best encoding.Optimizing FSM <FSM_12> on signal <state0[1:4]> with speed1 encoding.------------------- State | Encoding------------------- 000   | 1000 001   | 0100 010   | 0010 011   | 0001-------------------Analyzing FSM <FSM_11> for best encoding.Optimizing FSM <FSM_11> on signal <state[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000   | 00 001   | 01 010   | 10-------------------Analyzing FSM <FSM_10> for best encoding.Optimizing FSM <FSM_10> on signal <s5[1:1]> with gray encoding.------------------- State | Encoding------------------- 0000  | 0 0001  | 1-------------------Analyzing FSM <FSM_9> for best encoding.Optimizing FSM <FSM_9> on signal <s4[1:1]> with gray encoding.------------------- State | Encoding------------------- 0000  | 0 0001  | 1-------------------Analyzing FSM <FSM_8> for best encoding.Optimizing FSM <FSM_8> on signal <s3[1:2]> with gray encoding.------------------- State | Encoding------------------- 0000  | 00 0001  | 01 0010  | 11-------------------Analyzing FSM <FSM_7> for best encoding.Optimizing FSM <FSM_7> on signal <s2[1:1]> with gray encoding.------------------- State | Encoding------------------- 0000  | 0 0001  | 1-------------------Analyzing FSM <FSM_6> for best encoding.Optimizing FSM <FSM_6> on signal <s1[1:1]> with gray encoding.------------------- State | Encoding------------------- 0000  | 0 0001  | 1-------------------Analyzing FSM <FSM_5> for best encoding.Optimizing FSM <FSM_5> on signal <t5[1:2]> with sequential encoding.------------------- State | Encoding------------------- 0000  | 00 0001  | 01 0010  | 10-------------------Analyzing FSM <FSM_4> for best encoding.Optimizing FSM <FSM_4> on signal <t4[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 0000  | 10000 0001  | 01000 0010  | 00100 0011  | 00010 0100  | 00001-------------------Analyzing FSM <FSM_3> for best encoding.Optimizing FSM <FSM_3> on signal <t3[1:2]> with gray encoding.------------------- State | Encoding------------------- 0000  | 00 0001  | 01 0010  | 11-------------------Analyzing FSM <FSM_2> for best encoding.Optimizing FSM <FSM_2> on signal <t2[1:1]> with gray encoding.------------------- State | Encoding------------------- 0000  | 0 0001  | 1-------------------Analyzing FSM <FSM_1> for best encoding.Optimizing FSM <FSM_1> on signal <t1[1:1]> with gray encoding.------------------- State | Encoding------------------- 0000  | 0 0001  | 1
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