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| Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 0000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_7> for signal <s2>. ----------------------------------------------------------------------- | States | 2 | | Transitions | 4 | | Inputs | 2 | | Outputs | 2 | | Clock | clk (rising_edge) | | Clock enable | $n0003 (positive) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 0000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_8> for signal <s3>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 5 | | Inputs | 3 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 0000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_9> for signal <s4>. ----------------------------------------------------------------------- | States | 2 | | Transitions | 3 | | Inputs | 1 | | Outputs | 2 | | Clock | clk (rising_edge) | | Clock enable | $n0013 (positive) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 0000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_10> for signal <s5>. ----------------------------------------------------------------------- | States | 2 | | Transitions | 4 | | Inputs | 2 | | Outputs | 2 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 0000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <reset>. Found 1-bit register for signal <sload>. Found 1-bit register for signal <sclk>. Found 8-bit adder for signal <$n0026> created at line 41. Found 8-bit adder for signal <$n0027> created at line 105. Found 8-bit up counter for signal <sa>. Found 8-bit register for signal <sb>. Found 8-bit up counter for signal <sc>. Found 8-bit register for signal <sd>. Summary: inferred 5 Finite State Machine(s). inferred 2 Counter(s). inferred 19 D-type flip-flop(s). inferred 2 Adder/Subtractor(s).Unit <serial> synthesized.Synthesizing Unit <ICX229>. Related source file is "ICX229.v".INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state1> of Case statement line 108 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can: - add an 'init' attribute on signal <state1> (optimization is then done without any risk) - use the attribute 'signal_encoding user' to avoid onehot optimization - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization Found finite state machine <FSM_11> for signal <state>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 5 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_12> for signal <state0>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 4 | | Inputs | 0 | | Outputs | 4 | | Clock | clk (rising_edge) | | Clock enable | $n0008 (positive) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_13> for signal <state1>. ----------------------------------------------------------------------- | States | 8 | | Transitions | 8 | | Inputs | 0 | | Outputs | 10 | | Clock | clk (rising_edge) | | Clock enable | $n0012 (positive) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_14> for signal <state2>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 4 | | Inputs | 0 | | Outputs | 4 | | Clock | clk (rising_edge) | | Clock enable | $n0021 (positive) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_15> for signal <state3>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 3 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_16> for signal <state4>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 58 | | Inputs | 15 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_17> for signal <state5>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 12 | | Inputs | 7 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_18> for signal <state7>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 37 | | Inputs | 11 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_19> for signal <state8>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 5 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_20> for signal <state10>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 27 | | Inputs | 10 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_21> for signal <state11>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 5 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_22> for signal <state13>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 43 | | Inputs | 14 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_23> for signal <state14>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 12 | | Inputs | 8 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_24> for signal <state16>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 10 | | Inputs | 4 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_25> for signal <state17>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 10 | | Inputs | 4 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_26> for signal <state18>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 10 | | Inputs | 4 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <h1>. Found 1-bit register for signal <h2>. Found 1-bit register for signal <sub>. Found 1-bit register for signal <r>. Found 1-bit register for signal <v1>. Found 1-bit register for signal <v2>. Found 1-bit register for signal <v3>.⌨️ 快捷键说明
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