top.syr

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "ICX229.v"
Module <ICX229> compiled
Compiling verilog file "serial.v"
Module <serial> compiled
Compiling verilog file "VSP2232.v"
Module <VSP2232> compiled
Compiling verilog file "clk4.v"
Module <clk4> compiled
Compiling verilog file "shuju.v"
Module <shuju> compiled
Compiling verilog file "top.vf"
Module <top> compiled
No errors in compilation
Analysis of file <"top.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <top>.
Module <top> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <top>.
Analyzing module <ICX229>.
Module <ICX229> is correct for synthesis.
 
Analyzing module <serial>.
Module <serial> is correct for synthesis.
 
Analyzing module <VSP2232>.
Module <VSP2232> is correct for synthesis.
 
Analyzing module <shuju>.
Module <shuju> is correct for synthesis.
 
Analyzing module <clk4>.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 51: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <clk4> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <clk4>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <clk4>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <clk4>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <clk4>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <clk4>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk4>.
    Related source file is "clk4.v".
Unit <clk4> synthesized.


Synthesizing Unit <shuju>.
    Related source file is "shuju.v".
    Found finite state machine <FSM_0> for signal <zhuangtai>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 3                                              |
    | Clock              | sclk (falling_edge)                            |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <sdata>.
    Found 5-bit adder for signal <$n0007> created at line 17.
    Found 5-bit register for signal <count>.
    Found 16-bit register for signal <datain>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <shuju> synthesized.


Synthesizing Unit <VSP2232>.
    Related source file is "VSP2232.v".
    Found finite state machine <FSM_1> for signal <t1>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 3                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <t2>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 3                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_3> for signal <t3>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 1                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_4> for signal <t4>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 10                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_5> for signal <t5>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <shp>.
    Found 1-bit register for signal <adcck>.
    Found 1-bit register for signal <clpdm>.
    Found 1-bit register for signal <pblk>.
    Found 1-bit register for signal <clpob>.
    Found 1-bit register for signal <shd>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0033> created at line 83.
    Found 4-bit adder for signal <$n0038> created at line 23.
    Found 4-bit adder for signal <$n0039> created at line 53.
    Found 15-bit adder for signal <$n0041> created at line 118.
    Found 15-bit adder for signal <$n0042> created at line 169.
    Found 4-bit adder for signal <$n0043>.
    Found 4-bit register for signal <va>.
    Found 4-bit register for signal <vb>.
    Found 4-bit register for signal <vc>.
    Found 15-bit register for signal <vd>.
    Found 15-bit register for signal <ve>.
    Summary:
	inferred   5 Finite State Machine(s).
	inferred  48 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred   4 Multiplexer(s).
Unit <VSP2232> synthesized.


Synthesizing Unit <serial>.
    Related source file is "serial.v".
    Found finite state machine <FSM_6> for signal <s1>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 3                                              |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |