bootcoder.v

来自「这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对」· Verilog 代码 · 共 16 行

module bootcoder(b_i,as_o,ov_o,te_o,sub_valid);
parameter length=8;
input[2:0] b_i;// bh is the high bit, br is the current bit,bl is the low bit
output as_o,ov_o,te_o,sub_valid;
reg as_o,ov_o,te_o;  //as=0 add, as=1 sub ;ov =0 0, ov=1 a; te=0 0,te=1 2a;

always @(b_i)
begin
//get control signal
    as_o<=b_i[2];
    ov_o<=b_i[1]^b_i[0];
    te_o<=((~b_i[2])&b_i[1]&b_i[0])|(b_i[2]&(~b_i[0]|b_i[1]));   
end
assign sub_valid= as_o &(ov_o|te_o);
endmodule