mcucpld.map.rpt

CPLD程序

; Average fan-out      ; 2.16                 ;
+----------------------+----------------------+


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                 ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |MCUCPLD                   ; 32         ; 42   ; |MCUCPLD            ; work         ;
+----------------------------+------------+------+---------------------+--------------+


+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; SA[0]                                               ; Equal0              ; yes                    ;
; SA[1]                                               ; Equal0              ; yes                    ;
; SA[2]                                               ; Equal0              ; yes                    ;
; SA[3]                                               ; Equal0              ; yes                    ;
; SA[4]                                               ; Equal0              ; yes                    ;
; SA[5]                                               ; Equal0              ; yes                    ;
; SA[6]                                               ; Equal0              ; yes                    ;
; SA[7]                                               ; Equal0              ; yes                    ;
; SB[0]                                               ; Equal0              ; yes                    ;
; SB[1]                                               ; Equal0              ; yes                    ;
; SB[2]                                               ; Equal0              ; yes                    ;
; SB[3]                                               ; Equal0              ; yes                    ;
; SB[4]                                               ; Equal0              ; yes                    ;
; SB[5]                                               ; Equal0              ; yes                    ;
; SB[6]                                               ; Equal0              ; yes                    ;
; SB[7]                                               ; Equal0              ; yes                    ;
; SC[0]                                               ; Equal0              ; yes                    ;
; SC[1]                                               ; Equal0              ; yes                    ;
; SC[2]                                               ; Equal0              ; yes                    ;
; SC[3]                                               ; Equal0              ; yes                    ;
; SC[4]                                               ; Equal0              ; yes                    ;
; SC[5]                                               ; Equal0              ; yes                    ;
; SC[6]                                               ; Equal0              ; yes                    ;
; SC[7]                                               ; Equal0              ; yes                    ;
; SD[0]                                               ; Equal0              ; yes                    ;
; SD[1]                                               ; Equal0              ; yes                    ;
; SD[2]                                               ; Equal0              ; yes                    ;
; SD[3]                                               ; Equal0              ; yes                    ;
; SD[4]                                               ; Equal0              ; yes                    ;
; SD[5]                                               ; Equal0              ; yes                    ;
; SD[6]                                               ; Equal0              ; yes                    ;
; SD[7]                                               ; Equal0              ; yes                    ;
; Number of user-specified and inferred latches = 32  ;                     ;                        ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Sep 19 10:56:04 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MCUCPLD -c MCUCPLD
Info: Found 2 design units, including 1 entities, in source file MCUCPLD.vhd
    Info: Found design unit 1: MCUCPLD-Arch
    Info: Found entity 1: MCUCPLD
Info: Elaborating entity "MCUCPLD" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at MCUCPLD.vhd(32): signal "SA" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at MCUCPLD.vhd(33): signal "SB" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at MCUCPLD.vhd(34): signal "SC" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at MCUCPLD.vhd(35): signal "SD" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at MCUCPLD.vhd(21): inferring latch(es) for signal or variable "SA", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at MCUCPLD.vhd(21): inferring latch(es) for signal or variable "SB", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at MCUCPLD.vhd(21): inferring latch(es) for signal or variable "SC", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at MCUCPLD.vhd(21): inferring latch(es) for signal or variable "SD", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "SD[0]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SD[1]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SD[2]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SD[3]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SD[4]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SD[5]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SD[6]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SD[7]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SC[0]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SC[1]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SC[2]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SC[3]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SC[4]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SC[5]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SC[6]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SC[7]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SB[0]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SB[1]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SB[2]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SB[3]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SB[4]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SB[5]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SB[6]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SB[7]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SA[0]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SA[1]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SA[2]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SA[3]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SA[4]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SA[5]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SA[6]" at MCUCPLD.vhd(21)
Info (10041): Inferred latch for "SA[7]" at MCUCPLD.vhd(21)
Info: Implemented 74 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 32 output pins
    Info: Implemented 32 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Allocated 157 megabytes of memory during processing
    Info: Processing ended: Fri Sep 19 10:56:07 2008
    Info: Elapsed time: 00:00:03