dividertest.v

32位元2進位除法器

module divider32 (Q, R, dataBD, dataSD, shift, loadBigD, loadSmallD, done, clear, clk);

input shift, loadBigD, loadSmallD, done, clear, clk;
input [63:0] dataBD;
input [31:0] dataSD;

output reg [31:0] Q, R;

reg [64:0] BD;
reg [32:0] SD;
//wire LSB;

//always @ (negedge clk) if (loadBigD) BD[8:1] <= dataBD + 8'd0;
always @ (negedge clk) if (loadSmallD) SD <= dataSD + 33'd0;

always @ (posedge clk & ~done) begin
if (BD[64:32] >= SD) begin 
BD[64:32] <= BD[64:32] - SD;
BD[0] <= 1;
end
else BD[0] <= 0;
end
    
always @ (negedge clk) begin
case ({shift, clear, done, loadBigD})
    4'b1000 : BD[64:1] <= BD[63:0];
    4'b0100 : begin
    BD <= 65'd0;
    SD <= 33'd0;
end
    4'b0010 : begin
        Q <= BD[31:0];
        R <= BD[63:32];
    end
    4'b0001 : BD[64:1] <= dataBD + 64'd0;
    default : BD <= BD;
endcase
end

endmodule