dtoplevel.v

来自「32位元2進位除法器」· Verilog 代码 · 共 19 行

module Dtoplevel (Q, R, dataBD, dataSD, clk, start, done1);

output done1;    
output [31:0] Q, R;
input [31:0] dataSD;
input [63:0] dataBD;
input clk, start;
wire k;

//module divider4test (Q, R, dataBD, dataSD, shift, loadBigD, loadSmallD, done, clear, clk);
//module Dcontrol (shift, loadBigD, loadSmallD, done, clear, clk, start);
wire shift, loadBigD, loadSmallD, done, clear;

divider32 datapath (Q, R, dataBD, dataSD, shift, loadBigD, loadSmallD, done, clear, clk);
Dcontrol controller (shift, loadBigD, loadSmallD, done, clear, clk, start);

assign done1 = done;

endmodule