dividercontrol.v

32位元2進位除法器

module Dcontrol (shift, loadBigD, loadSmallD, done, clear, clk, start);
    
output reg shift, loadBigD, loadSmallD, done, clear;
input clk, start;

`define idle 6'd0
`define init 6'd1

`define m1 6'd5
`define m2 6'd6
`define m3 6'd7
`define m4 6'd8
`define m5 6'd9
`define m6 6'd10
`define m7 6'd11
`define m8 6'd12
`define m9 6'd13
`define m10 6'd14
`define m11 6'd15
`define m12 6'd16
`define m13 6'd17
`define m14 6'd18
`define m15 6'd19
`define m16 6'd20
`define m17 6'd21
`define m18 6'd22
`define m19 6'd23
`define m20 6'd24
`define m21 6'd25
`define m22 6'd26
`define m23 6'd27
`define m24 6'd28
`define m25 6'd29
`define m26 6'd30
`define m27 6'd31
`define m28 6'd32
`define m29 6'd33
`define m30 6'd34
`define m31 6'd35
`define m32 6'd36

`define result 6'd40


reg [5:0] current;

always @ (posedge clk) begin

shift=0; loadBigD=0; loadSmallD=0; done=0; clear=0;

case (current)
    `idle : if (~start) 
       begin
          current <= `idle;
          clear = 1;
          done <= 1;
       end 
       else begin
       current <= `init;
       clear = 1;
       done <= 1;
       end  
    
    `init : begin
        current <= `m1;
        loadBigD=1; loadSmallD=1;
    end

    `m1,`m2,`m3,`m4,`m5,`m6,`m7,`m8,`m9,`m10,`m11,`m12,`m13,`m14,`m15,`m16,`m17,`m18,`m19,`m20,`m21,`m22,`m23,`m24,`m25,`m26,`m27,`m28,`m29,`m30,`m31 : begin
    current <= current+1;
    shift = 1;
end

`m32 : begin
    current <= `idle;
    //shift = 1;
    done = 1;
end

//`result : begin
//    current <= `idle;
//    done =1;
//end

default : current <= `idle;

endcase
end

endmodule