dividersim.v

来自「32位元2進位除法器」· Verilog 代码 · 共 25 行

module Sim;

reg clk, start;
reg [63:0] dataBD;
reg [31:0] dataSD;    

wire [31:0] Q, R;

Dtoplevel sim1 (Q, R, dataBD, dataSD, clk, start, done1);

initial
begin
    clk = 1'b0;
    start = 0;
    dataBD = 0;
    dataSD = 0;
    #100 start = 0;
    #100 start = 1;
    dataBD = 64'd56; dataSD = 32'd5;
    #100 start = 0;
end

always #50 clk = ~clk;

endmodule