memandrom.v

簡易MIPS CPU程式碼 此CPU包含 shift add sub and or stl beq lw sw 等功能

module memANDrom (memdata, clk, memread, memwrite, writedata, address);
 
 output [31:0] memdata;
 input clk, memread, memwrite;
 input [31:0] writedata, address;
 reg [31:0] memdata;
 
reg [31:0] mem_array [0:127];
wire [7:0] mem_offset;
reg instruction_mode;

assign mem_offset = address[9:2];  // drop 2 LSBs to get word offset

always @ (posedge clk)
begin
    mem_array[0] = { 6'd35, 5'd0, 5'd2, 16'd40 }; 
    mem_array[1] = { 6'd35, 5'd0, 5'd3, 16'd40 }; 
    mem_array[2] = { 6'd35, 5'd0, 5'd4, 16'd40 };
    //mem_array[3] = {6'd0, 5'd0, 5'd3, 5'd3, 5'd2, 6'd2};
    mem_array[3] = { 6'd0, 5'd3, 5'd2, 5'd5, 5'd0, 6'd32 };  // add 
    
//mem_array[4] = { 6'd2, 26'd3 };             // beq $6, $zero, -3  if not, go back 2
end
//if (8'd63 < mem_offest) instruction_mode = 1;
//else instruction_mode = 0;

//mem_array [31:0] [0] = { 6'd0, 5'd5, 5'd2, 5'd5, 5'd0, 6'd32 };
always @(memread or mem_offset or mem_array[mem_offset])
  begin
    if (memread == 1'b1)
    begin
        //case (mem_offset)
          //8'd0 : memdata = { 6'd35, 5'd0, 5'd2, 16'd4 };             // lw $2, 256($0)    r2=64
          //8'd1 : memdata = { 6'd43, 5'd0, 5'd2, 16'd0 };             // MEM[0] = $5          
      memdata = mem_array[mem_offset];
      //memdata = { 6'd0, 5'd5, 5'd2, 5'd5, 5'd0, 6'd32 };
      //default memdata = 32'hxxxxxxxx;
  //endcase
    end
      else memdata = 32'hxxxxxxxx;
  end

  // for WRITE operations
  always @(posedge clk)
  begin
    if (memwrite == 1'b1)
    begin
      mem_array[mem_offset] <= writedata;
    end
  end

  // initialize with some arbitrary values

  integer i;
  initial begin
    for (i=10; i<126; i=i+1) mem_array[i] = i;
  end
endmodule