instructiontest.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 25 行

module SimI;

reg clk, IRWrite;
reg [31:0] instr;

wire [5:0] opcode, funct;
wire [4:0] rs, rt, rd, shamt;
wire [15:0] immed;
wire [25:0] jumpoffset;

instruction ST (opcode, rs, rt, rd, shamt, funct, immed, jumpoffset, clk, instr, IRWrite);

initial
begin
    clk = 1'b0;
    IRWrite = 1'b0;
    instr = {6'd35, 5'd0, 5'd4, 16'd0};
    #50 IRWrite = 1'b1;
    #100 IRWrite = 1'b0;
end

always #50 clk = ~clk;

endmodule