instruction.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 30 行

module instruction(opcode, rs, rt, rd, shamt, funct, immed, jumpoffset, clk, instr, IRWrite);
    
output [5:0] opcode, funct;
output [4:0] rs, rt, rd, shamt;
output [15:0] immed;
output [25:0] jumpoffset;

reg [5:0] opcode, funct;
reg [4:0] rs, rt, rd, shamt;
reg [15:0] immed;
reg [25:0] jumpoffset;

input clk, IRWrite;
input [31:0] instr;

always @ (posedge clk) begin
if (IRWrite) begin
opcode <= instr[31:26];
rs <= instr[25:21];
rt <= instr[20:16];
rd <= instr[15:11];
shamt <= instr[10:6];
funct <= instr[5:0];
immed <= instr[15:0];
jumpoffset <= instr[25:0];
end
end

endmodule