controlunit.v

簡易MIPS CPU程式碼 此CPU包含 shift add sub and or stl beq lw sw 等功能

module controlUNIT(idle, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, CauseWrite, IntCause, EPCwrite, ALUSrcA, RegWrite, RegDst, ALUOp, PCSource, ALUSrcB, clk, opcode, reset);

output idle;
reg idle;
output PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, CauseWrite, IntCause, EPCwrite, ALUSrcA, RegWrite, RegDst;
reg PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, CauseWrite, IntCause, EPCwrite, ALUSrcA, RegWrite, RegDst;
output reg [1:0] ALUOp, PCSource, ALUSrcB;
 //[1:0] ALUOp, PCSource, ALUSrcB;

input clk, reset;
input [5:0] opcode;



parameter [5:0] 
reset_state = 6'b000000,
instr_fetch = 6'b000001,
instr_decode =6'b000010,
EACBJ =6'b000011,
memORR =6'b000100,
mem_completion =6'b000101;

reg [5:0] pstate, nstate;

always @ (opcode or reset or pstate) begin
    PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b0; RegDst= 1'b0;
ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b00;
//idle = 1'b1;
//if (idle) pstate = reset_state;
case (pstate)
    reset_state : begin
if (!reset) begin
nstate = instr_fetch;  
PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b0; RegDst= 1'b0;
ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b00;
idle = 1'b0;
end
end
    instr_fetch : begin
        nstate = instr_decode;
        PCWriteCond = 1'b0; PCWrite= 1'b1; IorD= 1'b0; MemRead= 1'b1; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b1; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b0; RegDst= 1'b0;
        ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b01;
        idle = 1'b0;
    end
    instr_decode : begin
        nstate = EACBJ;
        PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b0; RegDst= 1'b0;
        ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b11;
        idle = 1'b0;
    end
    EACBJ : begin
        case (opcode)
            6'b100011 : begin // load word
                nstate = memORR;
                PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b1; RegWrite= 1'b0; RegDst= 1'b0;
                ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b10;
                idle = 1'b0;
            end
            6'b000000 : begin // R type
                nstate = memORR;
                PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b1; RegWrite= 1'b0; RegDst= 1'b0;
                ALUOp = 2'b10; PCSource= 2'b00; ALUSrcB= 2'b00;
                idle = 1'b0;
            end
            6'b000100 : begin // BEQ
                nstate = instr_fetch;
                PCWriteCond = 1'b1; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b1; RegWrite= 1'b0; RegDst= 1'b0;
                ALUOp = 2'b01; PCSource= 2'b01; ALUSrcB= 2'b00;
                idle = 1'b1;
            end
            6'b101011 : begin // store word
                nstate = memORR;
                PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b1; RegWrite= 1'b0; RegDst= 1'b0;
                ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b10;
                idle = 1'b0;
            end
            6'b000010 : begin // jump
                nstate = instr_fetch;
                PCWriteCond = 1'b0; PCWrite= 1'b1; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b0; RegDst= 1'b0;
                ALUOp = 2'b00; PCSource= 2'b10; ALUSrcB= 2'b00;
                idle = 1'b1;
           end
       default 
       begin
           idle = 1'b1;
       nstate = reset_state;
   end
   endcase
   end
    memORR : begin
        case (opcode)
            6'b100011 : begin // lW
                nstate = mem_completion;
                PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b1; MemRead= 1'b1; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b0; RegDst= 1'b0;
                ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b00;
            end
            6'b000000 : begin // r type
                nstate = instr_fetch;
                PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b1; RegDst= 1'b1;
                ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b00;
                idle = 1'b1;
            end
            6'b101011 : begin // SW
                nstate = instr_fetch;
                PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b1; MemRead= 1'b0; MemWrite= 1'b1; MemtoReg= 1'b0; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b0; RegDst= 1'b0;
                ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b00;
                idle = 1'b1;
            end
            default begin
           idle = 1'b1;
       nstate = reset_state;
   end
    endcase
end
    mem_completion : begin 
    nstate = instr_fetch;
    PCWriteCond = 1'b0; PCWrite= 1'b0; IorD= 1'b0; MemRead= 1'b0; MemWrite= 1'b0; MemtoReg= 1'b1; IRWrite= 1'b0; CauseWrite= 1'b0; IntCause= 1'b0; EPCwrite= 1'b0; ALUSrcA= 1'b0; RegWrite= 1'b1; RegDst= 1'b0;
    ALUOp = 2'b00; PCSource= 2'b00; ALUSrcB= 2'b00;
    idle = 1'b1;
end
default begin
           idle = 1'b1;
       nstate = reset_state;
   end
endcase
end





always @( negedge clk )
begin
if( !reset ) begin
pstate <= nstate;
end
else begin
    idle <= 1'b1;
pstate <= reset_state;
end
end


endmodule