aluctl.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 48 行

//-----------------------------------------------------------------------------
// Title         : ALU Control Unit
//-----------------------------------------------------------------------------

module alu_ctl(ALUOp, Funct, ALUOperation);
    input [1:0] ALUOp;
    input [5:0] Funct;
    output [4:0] ALUOperation;
    reg    [4:0] ALUOperation;

    // symbolic constants for instruction function code
    parameter F_add = 6'd32;
    parameter F_sub = 6'd34;
    parameter F_and = 6'd36;
    parameter F_or  = 6'd37;
    parameter F_slt = 6'd42;
    parameter F_shiftr = 6'd2;
    parameter F_shiftl = 6'd0;
    // symbolic constants for ALU Operations
    parameter ALU_add = 5'b00010;
    parameter ALU_sub = 5'b00110;
    parameter ALU_and = 5'b00000;
    parameter ALU_or  = 5'b00001;
    parameter ALU_slt = 5'b00111;
    parameter ALU_PCcounter = 5'b00100;  // new setting for PC
    //parameter ALU_shift = 5'b00011;
    parameter ALU_shiftr = 5'b10011;
    parameter ALU_shiftl = 5'b00011;
    always @(ALUOp or Funct)
    begin
        case (ALUOp) 
            2'b00 : ALUOperation = ALU_PCcounter;   // new setting for PC
            2'b01 : ALUOperation = ALU_sub;  // for branch
            2'b10 : case (Funct) 
                        F_add : ALUOperation = ALU_add;
                        F_sub : ALUOperation = ALU_sub;
                        F_and : ALUOperation = ALU_and;
                        F_or  : ALUOperation = ALU_or;
                        F_slt : ALUOperation = ALU_slt;
                        F_shiftr : ALUOperation = ALU_shiftr;
                        F_shiftl : ALUOperation = ALU_shiftl;
                        default ALUOperation = 3'bxxx;
                    endcase
            default ALUOperation = 3'bxxx;
        endcase
    end
endmodule