alusim.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 19 行

module simALU;

wire zero;
wire [31:0] result;

reg [2:0] ctl;
reg [31:0] a, b;
   
alu aaa (ctl, a, b, result, zero);


initial
begin
    ctl = 3'b100;
    a = 32'd0;
    b = 32'd4;
end
endmodule