controlsim.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 28 行

module SIMC;

wire PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, CauseWrite, IntCause, EPCwrite, ALUSrcA, RegWrite, RegDst;
// PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, CauseWrite, IntCause, EPCwrite, ALUSrcA, RegWrite, RegDst;
wire [1:0] ALUOp, PCSource, ALUSrcB;
//reg [1:0] ALUOp, PCSource, ALUSrcB;

reg clk, reset;
reg [5:0] opcode;
wire idle;

controlUNIT CCC (idle, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, CauseWrite, IntCause, EPCwrite, ALUSrcA, RegWrite, RegDst, ALUOp, PCSource, ALUSrcB, clk, opcode, reset);

initial
begin
    clk = 1'b0;
    reset = 1'b0;
    # 100 reset = 1'b1;
    #50 opcode = 6'b000010;
    # 50 reset = 1'b0;
    //#300 reset= 1'b1;
    //opcode = 6'b000000;
end

always #50 clk = ~clk;

endmodule