topsim.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 23 行

module simTOP;
 
reg clk, reset;
reg [31:0] instruction;
wire idle;
   
MIPSdatapath uu (idle, clk, reset, instruction);

initial
begin
    clk = 1'b0;
    reset = 1'b0;
    # 100 reset = 1'b1;
    //#50 opcode = 6'b000010;
    # 100 reset = 1'b0;
    //#300 reset= 1'b1;
    //opcode = 6'b000000;
end

always #50 clk = ~clk;

endmodule