mipsdatapath.v

簡易MIPS CPU程式碼 此CPU包含 shift add sub and or stl beq lw sw 等功能

module MIPSdatapath (idle, clk, reset, instruction);

input clk, reset;
input [31:0] instruction;
output idle;
//reg idle;

wire PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, CauseWrite, IntCause, EPCwrite, ALUSrcA, RegWrite, RegDst;
wire [1:0] ALUOp, PCSource, ALUSrcB;
wire [5:0] opcode;

controlUNIT control (idle, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, CauseWrite, IntCause, EPCwrite, ALUSrcA, RegWrite, RegDst, ALUOp, PCSource, ALUSrcB, clk, opcode, reset);

wire [31:0] MemData, Writedata, Address;
//wire MemRead, MemWrite;
wire [31:0] PCcounter, Bout;

memANDrom memory1 (MemData, clk, MemRead, MemWrite, Bout, Address);

wire [31:0] ALUout;

mux2 m21 ( IorD, PCcounter, ALUout, Address );

wire PCWrite11;
wire [31:0] d_in;

PC PC11 (reset, PCWrite11, clk, d_in, PCcounter);

wire [5:0] funct;
wire [4:0] rs, rt, rd, shamt;
wire [15:0] immed;
wire [25:0] jumpoffset;

instruction IR (opcode, rs, rt, rd, shamt, funct, immed, jumpoffset, clk, MemData, IRWrite);

wire [31:0] MDR_out;

MDR mdr1 (clk, MemData, MDR_out);

wire [31:0] writeTOreg;
mux2 m22 ( MemtoReg, ALUout, MDR_out, writeTOreg );

wire [4:0] Writeregister;

mux5 mm ( RegDst, rt, rd, Writeregister );

wire [31:0] RD1, RD2;

registers R1 (clk, RegWrite, rs, rt, Writeregister, RD1, RD2, writeTOreg);

wire [31:0] Aout;

reg32 AA (clk, RD1, Aout);


reg32 BB (clk, RD2, Bout);

wire [31:0] AtoALU;

mux2 m23 ( ALUSrcA, PCcounter, Aout, AtoALU );

wire [31:0] BtoALU, signEX, signEXshift;

mux4 M41 (BtoALU, ALUSrcB, Bout, 32'd4, signEX, signEXshift);

wire [4:0] ALUOperation;

alu_ctl ALUC (ALUOp, funct, ALUOperation);

wire [31:0] result;
wire zero;

alu alu1 (shamt, ALUOperation, AtoALU, BtoALU, result, zero);

and a1 (and1, zero, PCWriteCond);
or  o1 (PCWrite11, and1, PCWrite);


reg32 ALUout1 (clk, result, ALUout);

wire [31:0] toPC, shift2;

mux4 M42 (d_in, PCSource, result, ALUout, shift2, 32'd0);


wire [31:0] extend_immed; 
assign signEX = { {16{immed[15]}}, immed };

assign signEXshift = signEX << 2;

wire [27:0] SL2628;

assign SL2628 = {{jumpoffset}, 2'b00};

assign shift2 = {{PCcounter[31:28]},{SL2628}};

endmodule