testmux4.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 19 行

module SIMM;

reg [1:0] sel4;
reg [31:0] a, b, c, d;
wire [31:0] y;
mux4 MM (y, sel4, a, b, c, d);

initial
begin
    a = 32'd1;
    b = 32'd2;
    c = 32'd3;
    d = 32'd4;
    #50 sel4 = 2'b00;
    #40 sel4 = 2'b01;
    #30 sel4 = 2'b10;
    #20 sel4 = 2'b11;
end
endmodule