reg32.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 15 行

module reg32 (clk, d_in, d_out);
    input       	clk;
    input	[31:0]	d_in;
    output 	[31:0] 	d_out;
    reg 	[31:0]	 d_out;
   
    always @(posedge clk)
    begin
        //if (reset) d_out <= 0;
        d_out <= d_in;
    end

endmodule