alu.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 34 行

//-----------------------------------------------------------------------------
// Title         : ALU Behavioral Model
//-----------------------------------------------------------------------------

module alu(shamt, ctl, a, b, result, zero);
  input [4:0] ctl;
  input [31:0] a, b;
  output [31:0] result;
  output zero;
input [4:0] shamt;
  reg [31:0] result;
  reg zero;
// parameter ALU_PCcounter = 3'b100;  // new setting for PC
    //parameter ALU_shiftr = 5'b10011;
    //parameter ALU_shiftl = 5'b00011;
  always @(a or b or ctl)
  begin
    case (ctl)
      5'b00100 : result = a + b;  // for PC counter
      5'b00000 : result = a & b; // AND
      5'b00001 : result = a | b; // OR
      5'b00010 : result = a + b; // ADD
      5'b00110 : result = a - b; // SUBTRACT
      5'b00011 : result = b << shamt;
      5'b10011 : result = b >> shamt;
      5'b00111 : if (a < b) result = 32'd1; 
               else result = 32'd0; //SLT   branch   
      default : result = 32'hxxxxxxxx;
   endcase
   if (result == 32'd0) zero = 1'b1;
   else zero = 1'b0;
 end
endmodule