crc_tb.vhd

crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,

-------------------------------------------------------------------------------
-- 
-- $Revision: 1.7 $
-- $Date: 2003/12/31 02:16:41 $
--
-------------------------------------------------------------------------------
-- CRC Test Bench
-------------------------------------------------------------------------------
--
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--     FOR A PARTICULAR PURPOSE.
--     
--     (c) Copyright 2003 Xilinx, Inc.
--     All rights reserved.
--
---------------------------------------------------------------------
-- File Name: crc_tb.vhd
-- Author: Chris Borrelli
--
-- Description: CRC Test Bench
---------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

library work;
use work.crc_components.all;
use work.crc_functions.all;

entity testbench is
end testbench;

architecture testbench_arch of testbench is

  constant data_width    :  integer := 32;
  constant crc_width     :  integer := 32;
  constant poly          :  std_logic_vector(crc_width-1 downto 0) := "00000100110000010001110110110111";
  constant alligned_data :  std_logic := '0';
  constant insertcrc     :  std_logic := '0';
  constant residue       :  std_logic := '1';
  constant stripcrc      :  std_logic := '0';
  constant pipeline      :  std_logic := '1';
  constant back_to_back  :  std_logic := '0';
  constant trandata      :  std_logic := '1';
  constant trancrc       :  std_logic := '1';
  constant compcrc       :  std_logic := '1';
  constant crcinit       :  std_logic_vector(crc_width-1 downto 0) := "11111111111111111111111111111111";
  constant residue_value :  std_logic_vector(crc_width-1 downto 0) := "11000111000001001101110101111011";

  signal CLK              : std_logic;
  signal RST              : std_logic;

  signal LL_STIM_TX_DATA      : std_logic_vector(data_width-1 downto 0);
  signal LL_STIM_TX_REM       : std_logic_vector(rem_width_calc(data_width)-1 downto 0);
  signal LL_STIM_TX_SOF_N     : std_logic;
  signal LL_STIM_TX_SOP_N     : std_logic;
  signal LL_STIM_TX_EOP_N     : std_logic;
  signal LL_STIM_TX_EOF_N     : std_logic;
  signal LL_STIM_TX_SRC_RDY_N : std_logic;
  signal LL_STIM_TX_DST_RDY_N : std_logic;

  signal TX_CRC_DATA_DS       : std_logic_vector(data_width-1 downto 0);
  signal TX_CRC_REM_DS        : std_logic_vector(rem_width_calc(data_width)-1 downto 0);
  signal TX_CRC_SOF_N_DS      : std_logic;
  signal TX_CRC_EOF_N_DS      : std_logic;
  signal TX_CRC_SRC_RDY_N_DS  : std_logic;
  signal TX_CRC_DST_RDY_N_DS  : std_logic;

  signal RX_CRC_DATA_DS       : std_logic_vector(data_width-1 downto 0);
  signal RX_CRC_REM_DS        : std_logic_vector(rem_width_calc(data_width)-1 downto 0);
  signal RX_CRC_SOF_N_DS      : std_logic;
  signal RX_CRC_EOF_N_DS      : std_logic;
  signal RX_CRC_SRC_RDY_N_DS  : std_logic;
  signal RX_CRC_DST_RDY_N_DS  : std_logic;

  signal CRC_PASS_FAIL_N  : std_logic;
  signal CRC_VALID        : std_logic;

  component LL_STIM
    generic (
      C_DATA_WIDTH  : integer := 32;
      C_REM_WIDTH   : integer := 2
    );
    port (
      DATA        : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
      LL_REM      : out std_logic_vector(C_REM_WIDTH-1 downto 0);
      SOF_N       : out std_logic;
      SOP_N       : out std_logic;
      EOP_N       : out std_logic;
      EOF_N       : out std_logic;
      SRC_RDY_N   : out std_logic;
      DST_RDY_N   : in  std_logic;
      CLK         : in  std_logic;
      RESET       : in  std_logic
    );
  end component;

begin

  RX_CRC_DST_RDY_N_DS <= '0';

  clk_gen : process
  begin
    CLK <= '0';
    wait for 5 ns;
    CLK <= '1';
    wait for 5 ns;
  end process clk_gen;

  rst_gen : process
  begin
    rst <= '1';
    wait for 100 ns;
    rst <= '0';
    wait;
  end process rst_gen;

  ll_stim_i : LL_STIM
  generic map (
    C_DATA_WIDTH  =>   data_width,
    C_REM_WIDTH   =>   rem_width_calc(data_width))
  port map (
    CLK         =>   CLK,
    RESET       =>   RST,
    DATA        =>   LL_STIM_TX_DATA,
    LL_REM      =>   LL_STIM_TX_REM,
    SOF_N       =>   LL_STIM_TX_SOF_N,
    SOP_N       =>   LL_STIM_TX_SOP_N,
    EOP_N       =>   LL_STIM_TX_EOP_N,
    EOF_N       =>   LL_STIM_TX_EOF_N,
    SRC_RDY_N   =>   LL_STIM_TX_SRC_RDY_N,
    DST_RDY_N   =>   LL_STIM_TX_DST_RDY_N
  );

  tx_crc_i : TX_CRC
  generic map (
    data_width       =>   data_width,
    crc_width        =>   crc_width,
    poly             =>   poly,
    alligned_data    =>   alligned_data,
    insertcrc        =>   insertcrc,
    pipeline         =>   pipeline,
    trandata         =>   trandata,
    trancrc          =>   trancrc,
    compcrc          =>   compcrc,
    crcinit          =>   crcinit,
    residue_value    =>   residue_value,
    residue          =>   residue,
    stripcrc         =>   stripcrc
  )
  port map(
    DATA_DS          =>   TX_CRC_DATA_DS,
    REM_DS           =>   TX_CRC_REM_DS,
    SOF_N_DS         =>   TX_CRC_SOF_N_DS,
    EOF_N_DS         =>   TX_CRC_EOF_N_DS,
    SRC_RDY_N_DS     =>   TX_CRC_SRC_RDY_N_DS,
    DST_RDY_N_DS     =>   TX_CRC_DST_RDY_N_DS,
    DATA_US          =>   LL_STIM_TX_DATA,
    REM_US           =>   LL_STIM_TX_REM,
    SOF_N_US         =>   LL_STIM_TX_SOF_N,
    EOF_N_US         =>   LL_STIM_TX_EOF_N,
    SRC_RDY_N_US     =>   LL_STIM_TX_SRC_RDY_N,
    DST_RDY_N_US     =>   LL_STIM_TX_DST_RDY_N,
    RESET            =>   RST,
    CLK              =>   CLK
  );

  rx_crc_i : RX_CRC
  generic map (
    data_width       =>   data_width,
    crc_width        =>   crc_width,
    poly             =>   poly,
    alligned_data    =>   alligned_data,
    pipeline         =>   pipeline,
    back_to_back     =>   back_to_back,
    residue          =>   residue,
    stripcrc         =>   stripcrc,
    trandata         =>   trandata,
    trancrc          =>   trancrc,
    compcrc          =>   compcrc,
    crcinit          =>   crcinit,
    residue_value    =>   residue_value
  )
  port map(
    DATA_DS          =>   RX_CRC_DATA_DS,
    REM_DS           =>   RX_CRC_REM_DS,
    SOF_N_DS         =>   RX_CRC_SOF_N_DS,
    EOF_N_DS         =>   RX_CRC_EOF_N_DS,
    SRC_RDY_N_DS     =>   RX_CRC_SRC_RDY_N_DS,
    DST_RDY_N_DS     =>   RX_CRC_DST_RDY_N_DS,
    CRC_PASS_FAIL_N  =>   CRC_PASS_FAIL_N,
    CRC_VALID        =>   CRC_VALID,
    DATA_US          =>   TX_CRC_DATA_DS,
    REM_US           =>   TX_CRC_REM_DS,
    SOF_N_US         =>   TX_CRC_SOF_N_DS,
    EOF_N_US         =>   TX_CRC_EOF_N_DS,
    SRC_RDY_N_US     =>   TX_CRC_SRC_RDY_N_DS,
    DST_RDY_N_US     =>   TX_CRC_DST_RDY_N_DS,
    RESET            =>   RST,
    CLK              =>   CLK
  );

end testbench_arch;