extcomp.vhd

VHDL版的C8051核(C8051).evatronix公司的IP核

         
         --------------------------------------------------------------
         vector_driver :
         --------------------------------------------------------------
            process
               file     comp    : TEXT is in TESTPATH &
               TESTNAME & "/" & COMPFILE;
               variable row     : LINE;
               variable strobs  : NATURAL;
               variable deltas  : STRING(7 downto 1);
               variable stop    : TIME;
               variable vrst    : STD_LOGIC;
               variable vale    : STD_LOGIC;
               variable vpsen   : STD_LOGIC;
               variable vea     : STD_LOGIC;
               variable vp0     : STD_LOGIC_VECTOR(7 downto 0);
               variable vp1     : STD_LOGIC_VECTOR(7 downto 0);
               variable vp2     : STD_LOGIC_VECTOR(7 downto 0);
               variable vp3     : STD_LOGIC_VECTOR(7 downto 0);
            begin
               ----------------------------------------
               -- Reading first line
               ----------------------------------------
               if not ENDFILE(comp) then
                  READLINE(comp,row);
               end if;
            
               ----------------------------------------
               -- Reading rest of lines
               ----------------------------------------
               while not ENDFILE(comp) loop
                  test_end <= false;
                  READLINE(comp,row);
                  if row'length > 0 then
                     READ(row, strobs);
                     stop:=strobs*1 ns;
                     READ(row,deltas);
                     READ(row,vrst);
                     READ(row,vale);
                     READ(row,vpsen);
                     READ(row,vea);
                     READ(row,vp0);
                     READ(row,vp1);
                     READ(row,vp2);
                     READ(row,vp3);
                     if now > stop then
                        assert true
                           report "Detected a time in the " &
                           TESTNAME & "/" & COMPFILE &
                           " that is in the past."
                           severity error;
                     else
                        wait for stop-now;
                        srst   <= vrst;
                        sale   <= vale;
                        spsen  <= vpsen;
                        sea    <= vea;
                        sp0    <= vp0;
                        sp1    <= vp1;
                        sp2    <= vp2;
                        sp3    <= vp3;
                     end if;
                  end if;
               end loop;
            
               ----------------------------------------
               -- End of the comp file
               ----------------------------------------
               assert false
                  report "End of the standard test detected."
                  severity note;
               test_end <= true;
               wait;
            end process;
         
         
         --------------------------------------------------------------
         vector_comparator :
         --------------------------------------------------------------
            process (sample, test_end)
               file     diff   : TEXT is out TESTPATH &
               TESTNAME & "/" & DIFFFILE;
               variable row    : LINE;
               variable errors : NATURAL := 0;
            begin
               ----------------------------------
               -- Vectors comparing
               ----------------------------------
               if (sample'event and sample='1') then
                  if not test_end then
                     if srst/=rst then
                        errors:=errors+1;
                        WRITE(row,now);
                        WRITE(row,STRING'(" : signal rst is "));
                        WRITE(row,rst);
                        WRITE(row,STRING'(" but expected is "));
                        WRITE(row,srst);
                        WRITELINE(diff,row);
                     end if;
                     if sale/=ale then
                        errors:=errors+1;
                        WRITE(row,now);
                        WRITE(row,STRING'(" : signal ale is "));
                        WRITE(row,ale);
                        WRITE(row,STRING'(" but expected is "));
                        WRITE(row,sale);
                        WRITELINE(diff,row);
                     end if;
                     if spsen/=psen then
                        errors:=errors+1;
                        WRITE(row,now);
                        WRITE(row,STRING'(" : signal psen is "));
                        WRITE(row,psen);
                        WRITE(row,STRING'(" but expected is "));
                        WRITE(row,spsen);
                        WRITELINE(diff,row);
                     end if;
                     if sea/=ea then
                        errors:=errors+1;
                        WRITE(row,now);
                        WRITE(row,STRING'(" : signal ea is "));
                        WRITE(row,ea);
                        WRITE(row,STRING'(" but expected is "));
                        WRITE(row,sea);
                        WRITELINE(diff,row);
                     end if;
                     if sp0/=p0 then
                        errors:=errors+1;
                        WRITE(row,now);
                        WRITE(row,STRING'(" : port 0 is "));
                        WRITE(row,p0);
                        WRITE(row,STRING'(" but expected is "));
                        WRITE(row,sp0);
                        WRITELINE(diff,row);
                     end if;
                     if sp1/=p1 then
                        errors:=errors+1;
                        WRITE(row,now);
                        WRITE(row,STRING'(" : port 1 is "));
                        WRITE(row,p1);
                        WRITE(row,STRING'(" but expected is "));
                        WRITE(row,sp1);
                        WRITELINE(diff,row);
                     end if;
                     if sp2/=p2 then
                        errors:=errors+1;
                        WRITE(row,now);
                        WRITE(row,STRING'(" : port 2 is "));
                        WRITE(row,p2);
                        WRITE(row,STRING'(" but expected is "));
                        WRITE(row,sp2);
                        WRITELINE(diff,row);
                     end if;
                     if sp3/=p3 then
                        errors:=errors+1;
                        WRITE(row,now);
                        WRITE(row,STRING'(" : port 3 is "));
                        WRITE(row,p3);
                        WRITE(row,STRING'(" but expected is "));
                        WRITE(row,sp3);
                        WRITELINE(diff,row);
                     end if;
                  end if;
               end if;
            
               ----------------------------------
               -- Report writing
               ----------------------------------
               if test_end'event and test_end then
                  WRITE(row,now);
                  WRITE(row,STRING'
                           (" : End of the standard test detected."));
                  WRITELINE(diff,row);
                  if errors=0 then
                     assert false
                        report "The standard test " & TESTNAME &
                        " passed."
                        severity note;
                     WRITE(row,STRING'("The standard test passed."));
                     WRITELINE(diff,row);
                  else
                     assert false
                        report "The standard test " & TESTNAME &
                        " failed. Differences are in the file " &
                        TESTPATH & TESTNAME & "/" & DIFFFILE
                        severity note;
                     WRITE(row,STRING'("The standard test failed."));
                     WRITELINE(diff,row);
                     WRITE(row,errors);
                     WRITE(row,STRING'(" difference(s) detected"));
                     WRITELINE(diff,row);
                  end if;
               end if;
            end process;
         
         end generate;
      
      end block;
   
   end SIM;

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