extcomp.vhd

VHDL版的C8051核(C8051).evatronix公司的IP核

--*******************************************************************--
-- Copyright (c) 1999-2000  Evatronix Ltd.                           --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix S.A. immediately that you   --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : EXTCOMP.VHD
-- File contents        : Entity EXTERNAL_COMPARATOR
--                        Architecture SIM of EXTERNAL_COMPARATOR
-- Purpose              : Test vectors comparator
--
-- Destination library  : C8051_LIB
-- Dependencies         : IEEE.STD_LOGIC_1164
--                        STD.TEXTIO
--
-- Design Engineer      : M.B.
-- Quality Engineer     : M.B.
-- Version              : 3.01
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

library IEEE;
   use IEEE.STD_LOGIC_1164.all;
   use STD.TEXTIO.ALL;


   entity EXTERNAL_COMPARATOR is
      generic (
              MODE      : INTEGER := 2;  -- Comparator mode
                                         -- 0 - no occurrence
                                         -- 1 - the COMPFILE writer
                                         -- 2 - vectors comparator
              DUTY      : INTEGER := 90; -- recognize point (1-100%)
              TESTNAME  : STRING  := "default";
              TESTPATH  : STRING  := "tests/";
              COMPFILE  : STRING  := "simcomp.txt"; -- Compare file
              DIFFFILE  : STRING  := "simdiff.txt"  -- Differ. file
              );
      port (
           p0           : in  STD_LOGIC_VECTOR (7 DOWNTO 0);
           p1           : in  STD_LOGIC_VECTOR (7 DOWNTO 0);
           p2           : in  STD_LOGIC_VECTOR (7 DOWNTO 0);
           p3           : in  STD_LOGIC_VECTOR (7 DOWNTO 0);
           rst          : in  STD_LOGIC;
           ale          : in  STD_LOGIC;
           psen         : in  STD_LOGIC;
           ea           : in  STD_LOGIC;
           clk          : in  STD_LOGIC
           );
   end EXTERNAL_COMPARATOR;

--*******************************************************************--

   architecture SIM of EXTERNAL_COMPARATOR is
   
      signal test_end             : BOOLEAN;
      signal sample               : STD_LOGIC;
      signal srst,sale,spsen,sea  : STD_LOGIC;
      signal sp0,sp1,sp2,sp3      : STD_LOGIC_VECTOR (7 DOWNTO 0);
   
   
   --------------------------------------------------------------------
   -- Converts CHARACTER to STD_LOGIC bit :
   --------------------------------------------------------------------
      function TO_STD_LOGIC (data : CHARACTER) return STD_LOGIC is
         variable result : STD_LOGIC;
      begin
         case data is
            when 'U'    => result:='U';
            when 'X'    => result:='X';
            when '0'    => result:='0';
            when '1'    => result:='1';
            when 'Z'    => result:='Z';
            when 'W'    => result:='W';
            when 'L'    => result:='L';
            when 'H'    => result:='H';
            when '-'    => result:='-';
            when others => result:='X';
         end case;
         return result;
      end TO_STD_LOGIC;
   
   
   --------------------------------------------------------------------
   -- Converts STD_LOGIC bit to CHARACTER :
   --------------------------------------------------------------------
      function TO_CHARACTER (data : STD_LOGIC) return CHARACTER is
         variable result : CHARACTER;
      begin
         case data is
            when 'U'    => result:='U';
            when 'X'    => result:='X';
            when '0'    => result:='0';
            when '1'    => result:='1';
            when 'Z'    => result:='Z';
            when 'W'    => result:='W';
            when 'L'    => result:='L';
            when 'H'    => result:='H';
            when '-'    => result:='-';
            when others => result:='X';
         end case;
         return result;
      end TO_CHARACTER;
   
   
   --------------------------------------------------------------------
   -- Reads STD_LOGIC bit from string line :
   --------------------------------------------------------------------
      procedure READ (row : inout LINE; data : out STD_LOGIC) is
         variable char   : CHARACTER;
      begin
         while row'length>0 and row(row'left)=' ' loop
            READ(row, char);
         end loop;
         if row'length>0 then
            READ(row, char);
            data:=TO_STD_LOGIC(char);
         else
            data:='X';
         end if;
      end READ;
   
   
   --------------------------------------------------------------------
   -- Reads STD_LOGIC_VECTOR from string line :
   --------------------------------------------------------------------
      procedure READ (row : inout LINE; data : out STD_LOGIC_VECTOR) is
      begin
         for i in data'range loop
            READ(row, data(i));
         end loop;
      end READ;
   
   
   --------------------------------------------------------------------
   -- Writes STD_LOGIC bit to string line :
   --------------------------------------------------------------------
      procedure WRITE (row : inout LINE; data : in STD_LOGIC) is
         variable char : CHARACTER;
      begin
         char:=TO_CHARACTER(data);
         WRITE(row,char);
      end WRITE;
   
   
   --------------------------------------------------------------------
   -- Writes STD_LOGIC_VECTOR to string line :
   --------------------------------------------------------------------
      procedure WRITE (row : inout LINE; data : in STD_LOGIC_VECTOR) is
         variable char : CHARACTER;
      begin
         for i in data'range loop
            char:=TO_CHARACTER(data(i));
            WRITE(row,char);
         end loop;
      end WRITE;
   
   begin
   
   --------------------------------------------------------------------
   sample_generator :
   --------------------------------------------------------------------
      process (rst, clk)
         variable step     : TIME;
         variable last_clk : TIME;
      begin
         if (clk'event and clk='0') then
         
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               step:=now-last_clk;
               last_clk:=now;
               sample <= '0';
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            else
               sample <= '0', '1' after (step*DUTY/100);
            end if;
         
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   main : 
   --------------------------------------------------------------------
      block
      begin
      -----------------------------------------------------------------
      reader : 
      -----------------------------------------------------------------
         if MODE=2 generate