📄 extlatch.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2000 Evatronix Ltd. --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix S.A. immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : LATCH.VHD
-- File contents : Entity EXTERNAL_LATCH_REGISTER
-- Architecture SIM of EXTERNAL_LATCH_REGISTER
-- Purpose : Data latch register
--
-- Destination library : C8051_LIB
-- Dependencies : IEEE.STD_LOGIC_1164
--
-- Design Engineer : M.B.
-- Quality Engineer : M.B.
-- Version : 3.01
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity EXTERNAL_LATCH_REGISTER is
generic (
DATAWIDTH : NATURAL := 8
);
port (
strobe : in STD_LOGIC;
databusi : in STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
databuso : out STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end EXTERNAL_LATCH_REGISTER;
--**************************************************************************--
architecture SIM of EXTERNAL_LATCH_REGISTER is
begin
---------------------------------------------------------------------------
latch_proc :
---------------------------------------------------------------------------
process (strobe, databusi)
begin
if strobe='1' then
databuso <= TO_X01(databusi) after 1 ns;
end if;
end process;
end SIM;
--**************************************************************************--
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