extshift.vhd

VHDL版的C8051核(C8051).evatronix公司的IP核

--*******************************************************************--
-- Copyright (c) 1999-2000  Evatronix Ltd.                           --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix S.A. immediately that you   --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : EXTSHIFT.VHD
-- File contents        : Entity EXTERNAL_SHIFT_REGISTER
--                        Architecture SIM of EXTERNAL_SHIFT_REGISTER
-- Purpose              : Parametrisable clock generator
--
-- Destination library  : C8051_LIB
-- Dependencies         : IEEE.STD_LOGIC_1164
--
-- Design Engineer      : M.B.
-- Quality Engineer     : M.B.
-- Version              : 3.01
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

library IEEE;
   use IEEE.STD_LOGIC_1164.all;


   entity EXTERNAL_SHIFT_REGISTER is
      generic (
              DATAWIDTH : INTEGER := 8
              );
      port (
           clk          : in  STD_LOGIC;
           rst          : in  STD_LOGIC;
           we           : in  STD_LOGIC;
           oe           : in  STD_LOGIC;
           biti         : in  STD_LOGIC;
           bito         : out STD_LOGIC
           );
   end EXTERNAL_SHIFT_REGISTER;

--*******************************************************************--

   architecture SIM of EXTERNAL_SHIFT_REGISTER is
   
      signal shift_reg : STD_LOGIC_VECTOR(DATAWIDTH-1 DOWNTO 0);
   
   begin
   
   --------------------------------------------------------------------
   shifter :
   --------------------------------------------------------------------
      process (rst, clk)
      begin
         ----------------------------------------
         -- Asynchronous reset
         ----------------------------------------
         if rst='1' then
            shift_reg <= (OTHERS => '0');
            bito      <= 'Z';
         
         else
         ---------------------------------------
         -- Regster read:
         ---------------------------------------
            if oe='0' then
               bito <= shift_reg(0);
            else
               bito <= 'Z';
            end if;

            ----------------------------------------
            -- Synchronous write
            ----------------------------------------
            if (clk'event and clk='1') then
    
            -------------------------------------
            -- Regster shift
            -------------------------------------
                if (we='0' or oe='0') then
                   for i in 1 to DATAWIDTH-1 loop
                      shift_reg(i-1) <= shift_reg(i);
                   end loop;
                end if;
             
                   ----------------------------------
                   -- Regster write:
                   ----------------------------------
                if we='0' then
                   shift_reg(DATAWIDTH-1) <= TO_X01(biti);
                end if;
             
             end if;  
    	 end if;
      end process;
   
   
   end SIM;

--*******************************************************************--