extclock.vhd

VHDL版的C8051核(C8051).evatronix公司的IP核

--*******************************************************************--
-- Copyright (c) 1999-2000  Evatronix Ltd.                           --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix S.A. immediately that you   --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : EXTCLOCK.VHD
-- File contents        : Entity EXTERNAL_CLOCK_GENERATOR
--                        Architecture SIM of EXTERNAL_CLOCK_GENERATOR
-- Purpose              : Parametrisable clock generator
--
-- Destination library  : C8051_LIB
-- Dependencies         : IEEE.STD_LOGIC_1164
--
-- Design Engineer      : M.B.
-- Quality Engineer     : M.B.
-- Version              : 3.01
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

library IEEE;
   use IEEE.STD_LOGIC_1164.all;


   entity EXTERNAL_CLOCK_GENERATOR is
      generic (
              PERIOD    : TIME    := 100 ns; -- Clock pulse period
              DUTY      : INTEGER := 50;     -- Duty cycle (0-100%)
              SYNCSTART : TIME    := 1000 ns;
              SYNCSTOP  : TIME    := 2500 ns
              );
      port (                            
           reset        : in  STD_LOGIC;
           ale          : in  STD_LOGIC;
           clk          : out STD_LOGIC
           );
   end EXTERNAL_CLOCK_GENERATOR;

--*******************************************************************--

   architecture SIM of EXTERNAL_CLOCK_GENERATOR is
   
   signal clken     : STD_LOGIC;
   signal clken_rst : STD_LOGIC;
   signal sync      : STD_LOGIC;
   signal clock     : STD_LOGIC;
   
   begin
      
   --------------------------------------------------------------------
   clk_drv :
   --------------------------------------------------------------------
   clk <= clock and clken;
   
   --------------------------------------------------------------------
   main :
   --------------------------------------------------------------------
      process
         constant HALF_PERIOD : TIME := PERIOD*DUTY/100;
      begin
         ----------------------------------------
         -- Clock generator
         ----------------------------------------
         loop
            clock <= '0';
            wait for HALF_PERIOD;
            clock <= '1';
            wait for PERIOD-HALF_PERIOD;
         end loop;
      end process;

   --------------------------------------------------------------------
   clken_proc :
   --------------------------------------------------------------------
      process (clken_rst, ale)
         
      begin
      ----------------------------------------
      -- Asynchronous reset
      ----------------------------------------
         if clken_rst='1' then
            clken <= '1';
         else
         -------------------------------------
         -- Synchronous write
         -------------------------------------
            if ale'event and ale='0' then
               clken <= '0';
            end if;
         end if;
      end process;
    
   --------------------------------------------------------------------
   clken_rst_proc :
   --------------------------------------------------------------------
      process (clock, reset)
         
      begin
         if reset='1' then
            clken_rst <= '1';
         else
      ----------------------------------------
      -- Synchronous write
      ----------------------------------------
            if clock'event and clock='1' then
               clken_rst <= sync;
            end if;
         end if; 
      end process; 
      
   --------------------------------------------------------------------
   sync_write :
   --------------------------------------------------------------------
      sync <= '1','0' after SYNCSTART, '1' after SYNCSTOP;
   
   end SIM;

--*******************************************************************--