📄 chip8051.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : CHIP8051.VHD
-- File contents : Entity CHIP_C8051
-- Architecture STRUCTURAL of CHIP_C8051
-- Configuration C8051_STRUCTURE of CHIP_C8051
-- Purpose : Top-level structure of CHIP_C8051
--
-- Destination library : C8051_LIB
-- Dependencies : IEEE.STD_LOGIC_1164
--
-- Design Engineer : M.B.
-- Quality Engineer : M.B.
-- Version : 3.01
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library C8051_LIB;
entity CHIP_C8051 is
generic (
RAMSIZE : INTEGER := 8; -- RAM size index
ROMSIZE : INTEGER := 14; -- ROM size index
ROMFILE : STRING := "introm.hex"; -- Memory init file
FILEPATH : STRING := "tests/default/" -- Path to the init file
);
port (
-- Input ports
reset : in STD_LOGIC; -- Hardware reset input
xtal1 : in STD_LOGIC; -- Oscilator input
ea : in STD_LOGIC; -- External Access input
-- Bidirectional ports
p0 : inout STD_LOGIC_VECTOR(7 downto 0);
p1 : inout STD_LOGIC_VECTOR(7 downto 0);
p2 : inout STD_LOGIC_VECTOR(7 downto 0);
p3 : inout STD_LOGIC_VECTOR(7 downto 0);
-- Output ports
psen : out STD_LOGIC; -- Program Store Enable
ale : out STD_LOGIC; -- Address Latch Enable
xtal2 : out STD_LOGIC -- Oscilator output
);
end CHIP_C8051;
--*******************************************************************--
architecture STRUCTURAL of CHIP_C8051 is
-----------------------------------------------------------------
component C8051
-----------------------------------------------------------------
port (
-- Control signal inputs
clk : in STD_LOGIC; -- Global clock input
reset : in STD_LOGIC; -- Hardware reset input
ea : in STD_LOGIC; -- External Access input
-- Port inputs
p0i : in STD_LOGIC_VECTOR(7 downto 0);
p1i : in STD_LOGIC_VECTOR(7 downto 0);
p2i : in STD_LOGIC_VECTOR(7 downto 0);
p3i : in STD_LOGIC_VECTOR(7 downto 0);
-- Control signal outputs
psen : out STD_LOGIC; -- Ext. Program Store Enable
ale : out STD_LOGIC; -- Ext. Address Latch Enable
-- On-Chip Instrumentation interface
debugreq : in STD_LOGIC; -- debug mode request
debugstep : in STD_LOGIC; -- debug mode single-step
debugprog : in STD_LOGIC; -- debugger program select
debugack : out STD_LOGIC; -- debugger acknowledge signal
flush : out STD_LOGIC; -- branch instruction fetch
fetch : out STD_LOGIC; -- no-branch instruction fetch
acc : out STD_LOGIC_VECTOR(7 downto 0);
-- Port outputs
p0o : out STD_LOGIC_VECTOR(7 downto 0);
p1o : out STD_LOGIC_VECTOR(7 downto 0);
p2o : out STD_LOGIC_VECTOR(7 downto 0);
p3o : out STD_LOGIC_VECTOR(7 downto 0);
-- Program memory interface
romdatai : in STD_LOGIC_VECTOR( 7 downto 0);
romaddr : out STD_LOGIC_VECTOR(13 downto 0);
romoe : out STD_LOGIC; -- Memory output enable
-- Data memory interface
ramdatai : in STD_LOGIC_VECTOR(7 downto 0);
ramdatao : out STD_LOGIC_VECTOR(7 downto 0);
ramaddr : out STD_LOGIC_VECTOR(7 downto 0);
ramwe : out STD_LOGIC; -- Memory write enable
ramoe : out STD_LOGIC; -- Memory output enable
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatao : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : out STD_LOGIC_VECTOR(6 downto 0);
sfrwe : out STD_LOGIC; -- Register write enable
sfroe : out STD_LOGIC -- Register output enable
);
end component;
-----------------------------------------------------------------
component INTERNAL_OPEN_DRAIN
-----------------------------------------------------------------
generic (
WIDTH : INTEGER := 8
);
port (
input : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
output : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
);
end component;
-----------------------------------------------------------------
component INTERNAL_DATA_MEMORY
-----------------------------------------------------------------
generic (
DATAWIDTH : INTEGER := 8;
ADDRWIDTH : INTEGER := 8
);
port (
addrbus : in STD_LOGIC_VECTOR (ADDRWIDTH-1 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC;
databusi : in STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
databuso : out STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end component;
-----------------------------------------------------------------
component INTERNAL_PROGRAM_MEMORY
-----------------------------------------------------------------
generic (
DATAWIDTH : INTEGER := 8;
ADDRWIDTH : INTEGER := 12;
ROMFILE : STRING := "introm.hex"; -- Memory init file
FILEPATH : STRING := "tests/default/" -- Path to the init file
);
port (
addrbus : in STD_LOGIC_VECTOR (ADDRWIDTH-1 downto 0);
rd : in STD_LOGIC;
databus : out STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end component;
-----------------------------------------------------------------
component SPECIAL_FUNCTION_REGISTER
-----------------------------------------------------------------
generic (
SFR_ID : STD_LOGIC_VECTOR(6 downto 0) := "1111111";
SFR_RV : STD_LOGIC_VECTOR(7 downto 0) := "11111111"
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC;
sfroe : in STD_LOGIC;
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatao : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-----------------------------------------------------------------
component CHIP_OCI
-----------------------------------------------------------------
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- Internal program memory
addrbus : in STD_LOGIC_VECTOR (13 downto 0);
databusi : in STD_LOGIC_VECTOR (7 downto 0);
romoe : in STD_LOGIC;
--databuso : out STD_LOGIC_VECTOR (7 downto 0);
-- Internal data memory
ramaddr : in STD_LOGIC_VECTOR (7 downto 0);
ramdatai : in STD_LOGIC_VECTOR (7 downto 0);
ramdatao : in STD_LOGIC_VECTOR (7 downto 0);
ramwe : in STD_LOGIC; -- Memory write enable
ramoe : in STD_LOGIC; -- Memory output enable
-- SFR memory
sfraddr : in STD_LOGIC_VECTOR (6 downto 0);
sfrdatai : in STD_LOGIC_VECTOR (7 downto 0);
sfrdatao : in STD_LOGIC_VECTOR (7 downto 0);
sfrwe : in STD_LOGIC; -- Register write enable
sfroe : in STD_LOGIC; -- Register output enable
-- Debug control inputs
accreg : in STD_LOGIC_VECTOR (7 downto 0);
fetch : in STD_LOGIC; -- branch intruction fetch
flush : in STD_LOGIC; -- no-branch instruction fetch
debugack : in STD_LOGIC; -- debugger acknowlege
-- Debug control outputs
debugreq : out STD_LOGIC; -- debug mode request
debugstep : out STD_LOGIC; -- debug mode single step
debugprog : out STD_LOGIC -- debugger/user program
);
end component;
-- Chip port open drain inputs
signal p0drn : STD_LOGIC_VECTOR(7 downto 0);
signal p1drn : STD_LOGIC_VECTOR(7 downto 0);
signal p2drn : STD_LOGIC_VECTOR(7 downto 0);
signal p3drn : STD_LOGIC_VECTOR(7 downto 0);
-- Chip port drivers
signal p0drv : STD_LOGIC_VECTOR(7 downto 0);
signal p1drv : STD_LOGIC_VECTOR(7 downto 0);
signal p2drv : STD_LOGIC_VECTOR(7 downto 0);
signal p3drv : STD_LOGIC_VECTOR(7 downto 0);
-- Data memory interface
signal ramdatai : STD_LOGIC_VECTOR(7 downto 0);
signal ramdatao : STD_LOGIC_VECTOR(7 downto 0);
signal ramaddr : STD_LOGIC_VECTOR(RAMSIZE-1 downto 0);
signal ramwe : STD_LOGIC; -- Data file write enable
signal ramoe : STD_LOGIC; -- Data file output enable
-- Internal Program Memory interface
signal romdatai : STD_LOGIC_VECTOR(7 downto 0);
signal romaddr : STD_LOGIC_VECTOR(ROMSIZE-1 downto 0);
signal romoe : STD_LOGIC; -- Memory output enable
-- Special function register interface
signal sfrdatai : STD_LOGIC_VECTOR(7 downto 0);
signal sfrdatao : STD_LOGIC_VECTOR(7 downto 0);
signal sfraddr : STD_LOGIC_VECTOR(6 downto 0);
signal sfrwe : STD_LOGIC;
signal sfroe : STD_LOGIC;
-- OCI interface
signal debugreq : STD_LOGIC;
signal debugstep : STD_LOGIC;
signal debugprog : STD_LOGIC;
signal debugack : STD_LOGIC;
signal flush : STD_LOGIC;
signal fetch : STD_LOGIC;
signal acc : STD_LOGIC_VECTOR(7 downto 0);
begin
--------------------------------------------------------------------
-- Oscilator driver
--------------------------------------------------------------------
xtal_drv : xtal2 <= not xtal1;
--------------------------------------------------------------------
-- Chip port drivers
--------------------------------------------------------------------
p0_hand : p0drv <= TO_X01(p0);
p1_hand : p1drv <= TO_X01(p1);
p2_hand : p2drv <= TO_X01(p2);
p3_hand : p3drv <= TO_X01(p3);
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