chipsfr.vhd

VHDL版的C8051核(C8051).evatronix公司的IP核

--*******************************************************************--
-- Copyright (c) 1999-2001  Evatronix SA                             --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you     --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : CHIPSFR.VHD
-- File contents        : Entity SPECIAL_FUNCTION_REGISTER
--                        Architecture RTL of SPECIAL_FUNCTION_REGISTER
-- Purpose              : Synchronous Special Function Register
--
-- Destination library  : C8051_LIB
-- Dependencies         : IEEE.STD_LOGIC_1164
--
-- Design Engineer      : M.B.
-- Quality Engineer     : M.B.
-- Version              : 3.01
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

library IEEE;
   use IEEE.STD_LOGIC_1164.all;


   entity SPECIAL_FUNCTION_REGISTER is
      generic (
              SFR_ID    : STD_LOGIC_VECTOR(6 downto 0) := "1111111";
              SFR_RV    : STD_LOGIC_VECTOR(7 downto 0) := "11111111"
              );
      port (
           clk          : in  STD_LOGIC;
           reset        : in  STD_LOGIC;
           sfraddr      : in  STD_LOGIC_VECTOR(6 downto 0);
           sfrwe        : in  STD_LOGIC;
           sfroe        : in  STD_LOGIC;
           sfrdatai     : in  STD_LOGIC_VECTOR(7 downto 0);
           sfrdatao     : out STD_LOGIC_VECTOR(7 downto 0)
           );
   end SPECIAL_FUNCTION_REGISTER;

--*******************************************************************--

   architecture RTL of SPECIAL_FUNCTION_REGISTER is
   
      -- Special Function Register location and reset value
      -- constant SFR_ID   : STD_LOGIC_VECTOR(6 downto 0) := "1111111";
      -- constant SFR_RV   : STD_LOGIC_VECTOR(7 downto 0) := "11111111";
   
      -- Special Function Register
      signal sfr        : STD_LOGIC_VECTOR(7 DOWNTO 0);
   
   begin
   
   --------------------------------------------------------------------
   -- Special Function Register write
   --------------------------------------------------------------------
   sfr_write_proc :
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if reset='1' then
               sfr <= SFR_RV;
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Falling edge detection
               ----------------------------------
               if (sfrwe='1' and sfraddr=SFR_ID) then
                  sfr <= sfrdatai;
               end if;
            end if;
         end if;
      end process;


   --------------------------------------------------------------------
   -- Special Function Registers
   --------------------------------------------------------------------
   sfr_read :
   --------------------------------------------------------------------
      sfrdatao <=
         sfr; -- when sfraddr=SFR_ID else
   
   
   end RTL;
--*******************************************************************--