chipoci.vhd

VHDL版的C8051核(C8051).evatronix公司的IP核

--*******************************************************************--
-- Copyright (c) 1999-2001  Evatronix SA                             --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you     --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : CHIPOCI.VHD
-- File contents        : Entity CHIP_OCI
--                        Architecture SIM of CHIP_OCI
-- Purpose              : On-Chip Instrumentation
--
-- Destination library  : C8051_LIB
-- Dependencies         : IEEE.STD_LOGIC_1164
--
-- Design Engineer      : D.K.
-- Quality Engineer     : M.B.
-- Version              : 3.01
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

library IEEE;
   use IEEE.STD_LOGIC_1164.all;
   use STD.TEXTIO.ALL;

   entity CHIP_OCI is
      port (
           clk          : in  STD_LOGIC;
           rst          : in  STD_LOGIC;
           -- Internal Program memory
           addrbus      : in  STD_LOGIC_VECTOR (13 downto 0);
           databusi     : in  STD_LOGIC_VECTOR (7 downto 0);
           romoe        : in  STD_LOGIC;
           -- Internal Data memory
           ramaddr      : in  STD_LOGIC_VECTOR (7 downto 0);
           ramdatai     : in  STD_LOGIC_VECTOR (7 downto 0);
           ramdatao     : in  STD_LOGIC_VECTOR (7 downto 0);
           ramwe        : in  STD_LOGIC;  -- Memory write enable
           ramoe        : in  STD_LOGIC;  -- Memory output enable
           -- SFR memory
           sfraddr      : in  STD_LOGIC_VECTOR (6 downto 0);
           sfrdatai     : in  STD_LOGIC_VECTOR (7 downto 0);
           sfrdatao     : in  STD_LOGIC_VECTOR (7 downto 0);
           sfrwe        : in  STD_LOGIC;  -- Register write enable
           sfroe        : in  STD_LOGIC;  -- Register output enable
           -- Debug control inputs
           accreg       : in  STD_LOGIC_VECTOR (7 downto 0);
           fetch        : in  STD_LOGIC; -- branch intruction fetch
           flush        : in  STD_LOGIC; -- no-branch instruction fetch
           debugack     : in  STD_LOGIC; -- debugger acknowlege
           -- Debug control outputs
           debugreq     : out STD_LOGIC; -- debug mode request
           debugstep    : out STD_LOGIC; -- debug mode single step
           debugprog    : out STD_LOGIC  -- debugger/user program
           );
   end CHIP_OCI;



--*******************************************************************--

   architecture SIM of CHIP_OCI is
   begin
      --databuso  <= databusi;
      debugreq  <= '0';
      debugstep <= '0';
      
      debugprog <= '0';
   
   end SIM;

--*******************************************************************--