chippad.vhd

VHDL版的C8051核(C8051).evatronix公司的IP核

--*******************************************************************--
-- Copyright (c) 1999-2001  Evatronix SA                             --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you     --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : CHIPPAD.VHD
-- File contents        : Entity INTERNAL_OPEN_DRAIN
--                        Architecture SIM of INTERNAL_OPEN_DRAIN
-- Purpose              : Open drain buffer
--
-- Destination library  : C8051_LIB
-- Dependencies         : IEEE.STD_LOGIC_1164
--
-- Design Engineer      : M.B.
-- Quality Engineer     : M.B.
-- Version              : 3.01
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

library IEEE;
   use IEEE.STD_LOGIC_1164.all;


   entity INTERNAL_OPEN_DRAIN is
      generic (
              WIDTH     : INTEGER := 8
              );
      port (
           input        : in  STD_LOGIC_VECTOR(WIDTH-1 downto 0);
           output       : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
           );
   end INTERNAL_OPEN_DRAIN;

--*******************************************************************--

   architecture SIM of INTERNAL_OPEN_DRAIN is
   
   --------------------------------------------------------------------
   -- Converts STD_LOGIC bit to '0' or 'Z' value
   --------------------------------------------------------------------
      function TO_0Z (data : STD_LOGIC) return STD_LOGIC is
         variable result : STD_LOGIC;
      begin
         if (data='0') or (data='L') then
            result:='0';
         else
            result:='Z';
         end if;
         return result;
      end TO_0Z;
   
   begin
   
   --------------------------------------------------------------------
   drain :
   --------------------------------------------------------------------
      process (input)
      begin
         for i in input'range loop
            output(i) <= TO_0Z(input(i));
         end loop;
      end process;
   
   end SIM;
--*******************************************************************--