dw8051_intr_0.v

Verilog版的C51核(DW8051)

                                     0;

  assign tf0_clr  = ((ack_l == 1) & (i_src_l == `t0_src_0)) ? 1 : 0;
  			// TF0 flag is cleared in the int-ack cycle.

  assign tf1_clr  = ((ack_l == 1) & (i_src_l == `t1_src_0)) ? 1 : 0;
  			// TF1 flag is cleared in the int-ack cycle.


	// SFR Write process
  always @(posedge clk or negedge rst_n)
  begin : sfr_process
    if (rst_n == 0)
    begin 
      ie_reg <= 'b0;
      ip_reg <= 6'b000000;
      it0    <= 0;
      it1    <= 0;
      tr0    <= 0;
      tr1    <= 0;
      tf0    <= 0;
      tf1    <= 0;
      ie0    <= 0;
      ie1    <= 0;
      eicon_reg[7] <= 0;
    end
    else
    begin
      if (sfr_wr == 1)		// Software Update of registers
      begin 
        if (ie_cs == 1) ie_reg <= intr_data_in;
        if (ip_cs == 1) ip_reg <= intr_data_in[5:0];
        if (tcon_cs == 1)
        begin 
          it0 <= intr_data_in[0];
          it1 <= intr_data_in[2];
          tr0 <= intr_data_in[4];
          tr1 <= intr_data_in[6];
        end 
        if (eicon_cs == 1) eicon_reg[7] <= intr_data_in[7];
      end 

	// Hardware update of TF0 has greater priority than Software update.
           if (tf0_set == 1) tf0 <= 1;
      else if (tf0_clr == 1) tf0 <= 0;
      else if (tcon_wr == 1) tf0 <= intr_data_in[5];

	// Hardware update of TF1 has greater priority than Software update.
           if (tf1_set == 1) tf1 <= 1;
      else if (tf1_clr == 1) tf1 <= 0;
      else if (tcon_wr == 1) tf1 <= intr_data_in[7];

	// Hardware update of IE0 has greater priority than Software update.
           if (ie0_set == 1) ie0 <= 1;
      else if (ie0_clr == 1) ie0 <= 0;
      else if (tcon_wr == 1) ie0 <= intr_data_in[1];

	// Hardware update of IE1 has greater priority than Software update.
           if (ie1_set == 1) ie1 <= 1;
      else if (ie1_clr == 1) ie1 <= 0;
      else if (tcon_wr == 1) ie1 <= intr_data_in[3];
    end 
  end 

	// Aliases for IE register bits
  assign  ea  = ie_reg[7];
  assign  es0 = ie_reg[4];
  assign  et0 = ie_reg[1];
  assign  et1 = ie_reg[3];
  assign  et2 = ie_reg[5];
  assign  ex0 = ie_reg[0];
  assign  ex1 = ie_reg[2];

	// Aliases for IP register bits
  assign  ps0 = ip_reg[4];
  assign  pt0 = ip_reg[1];
  assign  pt1 = ip_reg[3];
  assign  pt2 = ip_reg[5];
  assign  px0 = ip_reg[0];
  assign  px1 = ip_reg[2];

	// Aliases for TCON register bits
  assign  tcon_reg[0] = it0;
  assign  tcon_reg[1] = ie0;
  assign  tcon_reg[2] = it1;
  assign  tcon_reg[3] = ie1;
  assign  tcon_reg[4] = tr0;
  assign  tcon_reg[5] = tf0;
  assign  tcon_reg[6] = tr1;
  assign  tcon_reg[7] = tf1;


  // external interrupt requests
  always @(posedge clk or negedge rst_n)
  begin : int_latch_process
    if (rst_n == 0)
    begin 
      x0_l1_n <= 0;
      x1_l1_n <= 0;
      x0_l2_n <= 0;
      x1_l2_n <= 0;
      x0_l3_n <= 0;
      x1_l3_n <= 0;
    end
    else
    begin
      x0_l1_n <= int0_n;	// Stage 1 synchronizers for int0_n and int1_n
      x1_l1_n <= int1_n;	// work at every clock
      if (cycle == `c4)
      begin 
        x0_l2_n <= x0_l1_n;	// Stage 2 and stage 3 synchronizers are
        x1_l2_n <= x1_l1_n;	// enabled only in clock phase C1 (i.e., end
        x0_l3_n <= x0_l2_n;	// of C4).
        x1_l3_n <= x1_l2_n;
      end 
    end 
  end 


  // Interrupt-Mask Logic
  assign  x0_req  = ie0 & ex0;
  assign  x1_req  = ie1 & ex1;
  assign  t0_req  = (tf0 | tf0_set) & et0;
  assign  t1_req  = (tf1 | tf1_set) & et1;
  assign  s0_req  = (ri0 | ti0)     & es0;
  assign  t2_req  = (tf2 | exf2)    & et2;

  // priorities of requests
  assign  x0_hp_req  = x0_req &  px0;
  assign  x0_lp_req  = x0_req & ~px0;
  assign  x1_hp_req  = x1_req &  px1;
  assign  x1_lp_req  = x1_req & ~px1;
  assign  t0_hp_req  = t0_req &  pt0;
  assign  t0_lp_req  = t0_req & ~pt0;
  assign  t1_hp_req  = t1_req &  pt1;
  assign  t1_lp_req  = t1_req & ~pt1;
  assign  t2_hp_req  = t2_req &  pt2;
  assign  t2_lp_req  = t2_req & ~pt2;
  assign  s0_hp_req  = s0_req &  ps0;
  assign  s0_lp_req  = s0_req & ~ps0;

  // interrupt sources
  
  // This is the high-priority queue
  assign hp_src  = (x0_hp_req == 1) ? `x0_src_0 :
                   (t0_hp_req == 1) ? `t0_src_0 :
                   (x1_hp_req == 1) ? `x1_src_0 :
                   (t1_hp_req == 1) ? `t1_src_0 :
                   (s0_hp_req == 1) ? `s0_src_0 :
                                      `t2_src_0;
				      
  // This is the low-priority queue 
  assign lp_src  = (x0_lp_req == 1) ? `x0_src_0 :
                   (t0_lp_req == 1) ? `t0_src_0 :
                   (x1_lp_req == 1) ? `x1_src_0 :
                   (t1_lp_req == 1) ? `t1_src_0 :
                   (s0_lp_req == 1) ? `s0_src_0 :
                                      `t2_src_0;

	// High priority interrupt request generation
  assign  hp_req  = (x0_hp_req |
                     x1_hp_req |
                     t0_hp_req |
                     t1_hp_req |
                     t2_hp_req |
                     s0_hp_req) & ea;

	// Low priority interrupt request generation
	// Note that this request is generated only when
	// there is no high pri interrupt yet, and when 
	// there isn't any highj-prio interrupt in progress 
	// (i.e., being serviced)
  assign  lp_req  = (x0_lp_req |
                     x1_lp_req |
                     t0_lp_req |
                     t1_lp_req |
                     t2_lp_req |
                     s0_lp_req) & ea & ~hp_req & ~iip1;


  // requests for all interrupts sampled at the begin of c3
  always @(posedge clk or negedge rst_n)
  begin : req_process
    if (rst_n == 0)
    begin 
      hp_req_l <= 0;
      lp_req_l <= 0;
    end
    else
    begin
      if (cycle == `c2)
      begin 
        hp_req_l <= hp_req;
        lp_req_l <= lp_req;
      end 
    end 
  end 


  // control signals for iip process
  assign  iip1_set = hp_req_l & int_ack;
  assign  iip1_clr = int_clr;
  assign  iip0_set = lp_req_l & int_ack;
  assign  iip0_clr = int_clr  & ~iip1;



  always @(posedge clk or negedge rst_n)
  begin : iip_process
    if  (rst_n == 0)
    begin 
      iip0 <= 0;
      iip1 <= 0;
    end
    else
    begin
           if (iip0_set == 1) iip0 <= 1;
      else if (iip0_clr == 1) iip0 <= 0;
           if (iip1_set == 1) iip1 <= 1;
      else if (iip1_clr == 1) iip1 <= 0;
    end 
  end 


  // compute output signals
  assign i_src       = (hp_req == 1) ? hp_src : lp_src;
  assign int_src     = i_src_l;
  assign int_req     = (hp_req_l & ~iip1) | (lp_req_l & ~iip0);
  assign intr_sfr_cs = ie_cs | ip_cs | tcon_cs | eicon_cs;

  // output mux
  assign intr_data_out = (ie_cs   == 1) ? ie_reg          :
                         (ip_cs   == 1) ? {2'b10, ip_reg} :
                         (tcon_cs == 1) ? tcon_reg        :
                                          {eicon_reg[7],7'b0000000};

  // output signals
  assign  ena_t0 = tr0;
  assign  ena_t1 = tr1;
  assign  smod1  = eicon_reg[7];


  // store source of actual interrupt
  always @(posedge clk or negedge rst_n)
  begin : i_src_latch_process
    if (rst_n == 0)
    begin 
      i_src_l <= 'b0;
    end
    else
    begin
      if (cycle == `c2) i_src_l <= i_src;
    end 
  end 


  // delay int_ack 1 cycle
  always @(posedge clk or negedge rst_n)
  begin : i_int_ack_process
    if (rst_n == 0)
    begin 
      ack_l <= 0;
    end
    else
    begin
      ack_l <= int_ack;
    end 
  end 


endmodule