dw8051_intr_0.v

Verilog版的C51核(DW8051)

// $Id: DW8051_intr_0.v,v 1.3 1996/07/30 14:33:40 uhlander Exp $
//------------------------------------------------------------------------------
//
//        This confidential and proprietary software may be used only
//     as authorized by a licensing agreement from synopsys Inc.
//     In the event of publication, the following notice is applicable:
//
//                    (C) COPYRIGHT 1996   SYNOPSYS INC.
//                          ALL RIGHTS RESERVED
//
//        The entire notice above must be reproduced on all authorized
//        copies.
//
// FILE: DW8051_intr_0.v
//
// AUTHOR: Ludwig Rieder
//
// ABSTRACT: DW8051 interrupt module for 6 interrupt sources (standard)
//           (Verilog version)
//
// MODIFICATION HISTORY:
//      L.Rieder        04.06.96        Verilog version created
//	L.Rieder	17.07.96	IP returns 11xxxxxxb now.
//	G.Uhlaender	29.07.96	missing assignment to port smod1 added
//	L.Rieder	30.07.96	IP returns 10xxxxxxb now.
//
//      Gina Ngo        11.20.96        Fixed star 38722: added header
//      Bala Needamangalam
//                      July 20,1999    Removed all DesignWare-Foundation 
//                                      license checkout commands.
//------------------------------------------------------------------------------



`include "./DW8051/DW8051_package.inc"
`include "./DW8051/DW8051_parameter.v"

module DW8051_intr_0 (clk,
		      rst_n,

                      // sfr bus signals:
                      sfr_addr,
                      intr_sfr_cs,
                      intr_data_out,
                      intr_data_in,
                      sfr_wr,
    
                      // signals from/to DW8051_cpu:
                      cycle,
                      int_req,
                      int_src,
                      int_ack,
                      int_clr,

                      // interrupt source signals:
                      int0_n,		// ext int 0
                      int1_n,		// ext int 1
                      tf0_set,		// timer 0 int
                      tf1_set,		// timer 1 int
                      ri0,		// receive  int
                      ti0,		// transmit int
                      tf2,		// timer 2 int
                      exf2,		// ext timer 2 int

                      // signals to timer module
                      ena_t0,
                      ena_t1,

                      // signal to serial port 1
                      smod1
		      );

 input clk;
 input rst_n;
 input [7:0]  sfr_addr;
 input [7:0]  intr_data_in;
 input sfr_wr;
 input [1:0]  cycle;
 input int_ack;
 input int_clr;
 input int0_n;
 input int1_n;
 input tf0_set;
 input tf1_set;
 input ri0;
 input ti0;
 input tf2;
 input exf2;
 output intr_sfr_cs;
 output [7:0]  intr_data_out;
 output  int_req;
 output [2:0]  int_src;
 output ena_t0;
 output ena_t1;
 output smod1;

//------------------------------------------------------------------------------
wire clk;
wire rst_n;
wire [7:0] sfr_addr;
wire [7:0] intr_data_in;
wire sfr_wr;
wire [1:0] cycle;
wire int_ack;
wire int_clr;
wire int0_n;
wire int1_n;
wire tf0_set;
wire tf1_set;
wire ri0;
wire ti0;
wire tf2;
wire exf2;
wire intr_sfr_cs;
wire [7:0] intr_data_out;
wire int_req;
wire [2:0] int_src;
wire ena_t0;
wire ena_t1;
wire smod1;

//---------------
// local signals:
//---------------
reg  [7:0] ie_reg;		// ie register
wire ea;
wire et0;
wire et1;
wire et2;
wire es0;
wire ex0;
wire ex1;
 
reg  [5:0] ip_reg;		// ip register
wire pt0;
wire pt1;
wire pt2;
wire ps0;
wire px0;
wire px1;
 
wire [7:0] tcon_reg;		// tcon register
reg  tf1;
reg  tr1;
reg  tf0;
reg  tr0;
reg  ie1;
reg  it1;
reg  ie0;
reg  it0;
 
reg  [7:0] eicon_reg;
wire eicon_cs;
 
wire ie_cs;			// chip select for ie-register
wire ip_cs;			// chip select for ip-register
wire tcon_cs;			// chip select for tcon-register
wire tcon_wr;
 
wire tf0_clr;
wire tf1_clr;
wire ie0_clr;
wire ie1_clr;
wire ie0_set;
wire ie1_set;
 
wire it0_set;
wire it1_set;
 
wire it0_clr;
wire it1_clr;
 
reg  ack_l;			// latched int_ack
 
reg  x0_l1_n;			// latched external interrupt 0
reg  x1_l1_n;			// latched external interrupt 1
reg  x0_l2_n;			// latched x0_l1_n
reg  x1_l2_n;			// latched x1_l1_n
reg  x0_l3_n;			// latched x0_l2_n
reg  x1_l3_n;			// latched x1_l2_n
 
wire x0_req;			// request from int0
wire x1_req;			// request from int1
wire t0_req;			// request from timer0
wire t1_req;			// request from timer1
wire t2_req;			// request from timer2
wire s0_req;			// request from serial port 0
 
wire x0_hp_req;			// high priority request from int0
wire x1_hp_req;			// high priority request from int1
wire t0_hp_req;			// high priority request from timer0
wire t1_hp_req;			// high priority request from timer1
wire t2_hp_req;			// high priority request from timer2
wire s0_hp_req;			// high priority request from serial port0
 
wire x0_lp_req;			// low priority request from int0
wire x1_lp_req;			// low priority request from int1
wire t0_lp_req;			// low priority request from timer0
wire t1_lp_req;			// low priority request from timer1
wire t2_lp_req;			// low priority request from timer2
wire s0_lp_req;			// low priority request from serial port0
 
wire [2:0] lp_src;		// source for low  priority requ.
wire [2:0] hp_src;		// source for high priority requ.
wire [2:0] i_src;		// source for active request
reg  [2:0] i_src_l;		// latched i_src
 
reg  iip0;			// low  priority interrupt in progress flag
reg  iip1;			// high priority interrupt in progress flag
wire iip0_set;
wire iip1_set;
wire iip0_clr;
wire iip1_clr;
 
wire hp_req;			// high priority request
wire lp_req;			// low  priority request
reg  hp_req_l;			// latched high priority request
reg  lp_req_l;			// latched low  priority request
 
 
// define interrupt source := interrupt_vector(5 downto 3)
`define x0_src_0 3'b000		// vector: 03h
`define x1_src_0 3'b010		// vector: 13h
`define t0_src_0 3'b001		// vector: 0Bh
`define t1_src_0 3'b011		// vector: 1Bh
`define t2_src_0 3'b101		// vector: 2Bh
`define s0_src_0 3'b100		// vector: 23h
 
//------------------------------------------------------------------------------

  // SFR Address decode
  assign ie_cs    = (sfr_addr == `ie_addr)    ? 1 : 0;
  assign ip_cs    = (sfr_addr == `ip_addr)    ? 1 : 0;
  assign tcon_cs  = (sfr_addr == `tcon_addr)  ? 1 : 0;
  assign eicon_cs = (sfr_addr == `eicon_addr) ? 1 : 0;

  // Defining the write-enable to TCON
  assign tcon_wr  = (tcon_cs & sfr_wr);

  // Software programming flags for set and reset of IT0
  assign it0_set  = (tcon_wr &  intr_data_in[0]);
  assign it0_clr  = (tcon_wr & ~intr_data_in[0]);

  // Software programming flags for set and reset of IT1
  assign it1_set  = (tcon_wr &  intr_data_in[2]);
  assign it1_clr  = (tcon_wr & ~intr_data_in[2]);

  assign ie0_set  = (cycle != `c1) ? 0                    :
                    (it0_clr == 1) ?  ~x0_l2_n            : // low-level sens.
                    (it0_set == 1) ? (~x0_l2_n & x0_l3_n) : // fall-edge sens.
                    (it0     == 0) ?  ~x0_l2_n            : // low-level sens.
                                     (~x0_l2_n & x0_l3_n);  // fall-edge sens.

  assign ie1_set  = (cycle != `c1) ? 0                    :
                    (it1_clr == 1) ?  ~x1_l2_n            : // low-level sens.
                    (it1_set == 1) ? (~x1_l2_n & x1_l3_n) : // fall-edge sens.
                    (it1     == 0) ?  ~x1_l2_n            : // low-level-sens.
                                     (~x1_l2_n & x1_l3_n);  // fall-edge sens.

  assign ie0_clr  = (((ack_l & it0) == 1) & (i_src_l == `x0_src_0)) ? 1 :
  						// int. ack cycle
                    (cycle != `c1) ? 0       :
                    (it0_set == 1) ? 0       :	// fall-edge sens & detected.
                    (it0_clr == 1) ? x0_l2_n :	// low-level sens & 1 detected
                    (it0     == 0) ? x0_l2_n :	// low-level sens & 1 detected
                                     0;

  assign ie1_clr  = (((ack_l & it1) == 1) & (i_src_l == `x1_src_0)) ? 1 :
  						// int. ack cycle
                    (cycle != `c1) ? 0       :
                    (it1_set == 1) ?      0  :	// fall-edge sens & detected
                    (it1_clr == 1) ? x1_l2_n :	// low-level sens & 1 detected
                    (it1     == 0) ? x1_l2_n :	// low-level sens & 1 detected