dw8051_biu.v

Verilog版的C51核(DW8051)

      bus_seq          <= `instr_rd_seq;
      ram_16bit_access <= 0;
      md_ld_n          <= 1;
      dec_md           <= 0;
      int_rom_rd_n     <= 1;
    end
    else
    begin
      if ((stop_mode_n == 0) | (idle_mode_n == 0))
      begin 
        //synchronous reset:
        mem_data_out     <= 'b0;
        mem_wr_n         <= 1;
        mem_rd_n         <= 1;
        mem_pswr_n       <= 1;
        mem_psrd_n       <= 1;
        ale_pos          <= 1;
        p0_mem_reg_n     <= 0;
        p0_addr_data_n   <= 0;
        if (ext_rom_access == 0) p2_mem_reg_n <= 0;
        instr_reg        <= 'b0;
        ram_access_rdy   <= 0;
        start_ram_seq    <= 0;
        bus_seq          <= `instr_rd_seq;
        ram_16bit_access <= 0;
        md_ld_n          <= 1;
        dec_md           <= 0;
        int_rom_rd_n     <= 1;
      end
      else
      begin
        if (wr_ram_addr_l == 1)			// _l sigal both for 8/16bit
        begin 
          md_ld_n  <= 0;			// load md counter
          if (wr_ram_addr_h == 1) ram_16bit_access <= 1;
          else                    ram_16bit_access <= 0;
        end 

        //-----------------------------------
        // process bus sequences:
        // (state decoder depending on cycle)
        //-----------------------------------
        case (bus_seq )

          //------------------
          // instruction read:
          //------------------
          `instr_rd_seq :
          begin
            case (cycle )
              `c1 : begin
                      if (ext_rom_access == 1)
                      begin 
                        p0_mem_reg_n   <= 1;		// p0 output is address
                        p0_addr_data_n <= 1;
                        p2_mem_reg_n   <= 1;		// for whole sequence
                        ale_pos        <= 0;		// start ale cycle
                      end
                      else
                      begin
                        p0_mem_reg_n <= 0;		// release port 0
                        p2_mem_reg_n <= 0;		// release port 2
                      end 
                      mem_addr  <= rom_addr;
                    end
              `c2 : begin
                      p0_addr_data_n <= 0;		// next read/write data
                      p0_mem_reg_n   <= 0;		// disable output driver
							// (port holds 0FFh)
                      if (ext_rom_access == 1)
                        mem_psrd_n   <= 0;		// start ext.ROM read
                      else
                        int_rom_rd_n <= 0;		// start int.ROM read
                    end
              `c3 : begin
                    end
              `c4 : begin
                      if (ext_rom_access == 1)
                           instr_reg  <= mem_data_in;
                      else instr_reg  <= int_rom_data_in;
                      ale_pos      <= 1;		// finish ale cycle
                      mem_psrd_n   <= 1;		// finish ext.ROM read
                      int_rom_rd_n <= 1;		// finish int.ROM read

                      // next bus sequence ram access ?
                      if (wr_ram == 1)
                      begin 
                        bus_seq       <= `ram_seq;
                        start_ram_seq <= 1;
                      end
                      else if (rd_ram == 1)
                      begin 
                        bus_seq       <= `ram_seq;
                        start_ram_seq <= 1;
                      end
                      else if (rd_rom == 1)
                           bus_seq <= `rd_rom_seq;
                      else bus_seq <= `instr_rd_seq;
                    end
           default: begin
                    end
            endcase
          end  //instr_rd_seq

          //------------------------
          // RAM read,RAM/ROM/write:
          //------------------------
          `ram_seq :
          begin
            case (cycle )
              `c1 : begin
                      if (start_ram_seq == 1)
                      begin 
                        start_ram_seq  <= 0;
                        p0_mem_reg_n   <= 1;		// p0 output is address
                        p0_addr_data_n <= 1;
                        if (ram_16bit_access == 1)
                             p2_mem_reg_n <= 1;		// for whole sequence
                        else p2_mem_reg_n <= 0;		// for whole sequence
                      end 
                      ale_pos      <= 0;		// start ale cycle
                      md_ld_n      <= 1;		// finish md load
                      dec_md       <= 0;
                      mem_addr     <= ram_addr;
                      mem_data_out <= data_out;		// in any way
                    end
              `c2 : begin
                      p0_addr_data_n <= 0;		// next cycle rd/wr data
                      if (rd_ram == 1)			// if ram read,
                        p0_mem_reg_n  <= 0;		// disable p0 output drv
                      if (md_zero == 1)
                      begin 
                        if (rd_ram == 1)
                          mem_rd_n  <= 0;		// start ram read
                        else
                        begin
                          if (wrs == 0)
                            mem_wr_n   <= 0;		// start ram write
                          else
                            mem_pswr_n <= 0;		// start rom write
                        end 
                      end 
                      if (md_end == 1)
                        ram_access_rdy <= 1;
                    end
              `c3 : begin
                      if (md_zero == 0)
                      begin 
                        if (md_end == 0)
                        begin 
                          if (rd_ram == 1)
                            mem_rd_n  <= 0;		// start ram read
                          else
                          begin
                            if (wrs == 0)
                              mem_wr_n   <= 0;		// start ram write
                            else
                              mem_pswr_n <= 0;		// start rom write
                          end 
                        end
                        else
                        begin				// md cycles done,
                          mem_wr_n   <= 1;		// finish RAM wr cycle
                          mem_pswr_n <= 1;		// finish ROM wr cycle
                          mem_rd_n   <= 1;		// finish RAM rd cycle
                          if (rd_ram == 1)
                            data_in  <= mem_data_in;
                        end 
                      end 
                    end
              `c4 : begin
                      if (md_end == 1)
                      begin 
                        bus_seq    <= `instr_rd_seq;	// next sequence: instr.
                        ale_pos    <= 1;		// finish ale cycle
                        mem_wr_n   <= 1;		// for md = 0
                        mem_pswr_n <= 1;		// for md = 0
                        mem_rd_n   <= 1;		// for md = 0
                        if ((md_zero == 1) & (rd_ram == 1))
                          data_in  <= mem_data_in;
                        ram_access_rdy  <= 0;
                      end
                      else
                        dec_md  <= 1;			// decrement md counter
                    end
           default: begin
                    end
            endcase  // cycle
          end  // ram_seq

          //----------
          // ROM read:
          //----------
          `rd_rom_seq :
          begin
            case (cycle )
              `c1 : begin
                      if (ext_rom_access_2 == 1)
                      begin 
                        p0_mem_reg_n   <= 1;		// p0 output is address
                        p0_addr_data_n <= 1;
                        p2_mem_reg_n   <= 1;		// for whole sequence
                        ale_pos        <= 0;		// start ale cycle
                      end
                      else
                      begin
                        p0_mem_reg_n <= 0;		// release port 0
                        p2_mem_reg_n <= 0;		// release port 2
                      end 
                      mem_addr <= ram_addr;		// !!
                    end
              `c2 : begin
                      p0_addr_data_n <= 0;		// next read/write data
                      p0_mem_reg_n   <= 0;		// disable output driver
							// (port holds 0FFh)
                      if (ext_rom_access_2 == 1)
                        mem_psrd_n   <= 0;		// start ext.ROM read
                      else
                        int_rom_rd_n <= 0;		// start int.ROM read
                    end
              `c4 : begin
                      if (ext_rom_access_2 == 1)
                        data_in  <= mem_data_in;	// get ext.ROM data
                      else
                        data_in  <= int_rom_data_in;	// get int.ROM data
                      ale_pos      <= 1;		// finish ale cycle
                      mem_psrd_n   <= 1;		// finish ext.ROM read
                      int_rom_rd_n <= 1;		// finish int.ROM read
                      bus_seq      <= `instr_rd_seq;	// back to normal
                    end
           default: begin
                    end
            endcase  // cycle
          end  // rd_rom_seq

          default: begin
                   end
        endcase  // bus_seq
      end 
    end  //posedge clk
  end  //main_biu_proc_pos


  always @(negedge clk)
  begin : main_biu_proc_neg
    if (rst_n == 0)
      ale_neg  <= 1;
    else
      ale_neg  <= ale_pos;
  end 

// mem_ale generation (1.5 clock cycles high):
  assign  mem_ale = (ale_pos | ale_neg);


endmodule