dw8051_op_decoder.v

Verilog版的C51核(DW8051)

                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_orl;
                              end
                     4'b0011: begin			// ORL direct, #imm8
                                itype      <=  11;
                                last_cycle <=  2;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  8;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_orl;
                              end
                     4'b0100: begin			// ORL A, #imm8
                                itype      <=  4;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_orl;
                              end
                     4'b0101: begin			// ORL A, direct
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_orl;
                              end
                     4'b0110,				// ORL A, @R0
		     4'b0111: begin			// ORL A, @R1
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  1;
                                alu_op     <= `alu_op_orl;
                              end
                     default: begin			// ORL A, [R0,R1,..R7]
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  1;
                                alu_op     <= `alu_op_orl;
                              end
                   endcase
                 end
        4'b0101: begin
                   case (op[3:0])
                     4'b0000: begin			// JNC rel
                                itype      <=  18;
                                last_cycle <=  2;
                              end
                     4'b0001: begin			// ACALL addr11
                                itype      <=  14;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// ANL direct, A
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  3;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_anl;
                              end
                     4'b0011: begin			// ANL direct, #imm8
                                itype      <=  11;
                                last_cycle <=  2;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  8;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_anl;
                              end
                     4'b0100: begin			// ANL A, #imm8
                                itype      <=  4;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_anl;
                              end
                     4'b0101: begin			// ANL A, direct
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_anl;
                              end
                     4'b0110,				// ANL A, @R0
		     4'b0111: begin			// ANL A, @R1
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  1;
                                alu_op     <= `alu_op_anl;
                              end
                     default: begin			// ANL A,[R0..R7]
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  1;
                                alu_op     <= `alu_op_anl;
                              end
                   endcase
                 end
        4'b0110: begin
                   case (op[3:0])			// JC rel_addr
                     4'b0000: begin
                                itype      <=  18;
                                last_cycle <=  2;
                                src        <=  1;
                              end
                     4'b0001: begin			// AJMP addr11
                                itype      <=  15;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// XRL direct, A
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  3;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_xrl;
                              end
                     4'b0011: begin			// XRL direct, #imm8
                                itype      <=  11;
                                last_cycle <=  2;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  8;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_xrl;
                              end
                     4'b0100: begin			// XRL A, #imm8
                                itype      <=  4;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_xrl;
                              end
                     4'b0101: begin			// XRL A, direct
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_xrl;
                              end
                     4'b0110,				// XRL A, @R0
		     4'b0111: begin			// XRL A, @R1
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  1;
                                alu_op     <= `alu_op_xrl;
                              end
                     default: begin			// XRL A, [R0..R7]
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  1;
                                alu_op     <= `alu_op_xrl;
                              end
                   endcase
                 end
        4'b0111: begin
                   case (op[3:0])
                     4'b0000: begin			// JNZ rel
                                itype      <=  18;
                                last_cycle <=  2;
                                src        <=  1;
                              end
                     4'b0001: begin			// ACALL addr11
                                itype      <=  14;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// ORL C, direct_bit
                                itype      <=  6;
                                src        <=  7;
                                src_cycle  <=  1;
                                alu_op     <= `alu_op_orlcb;
                              end
                     4'b0011: begin			// JMP @A+DPTR
                                itype      <=  17;
                                last_cycle <=  2;
                              end
                     4'b0100: begin			// MOV A,#imm8
                                itype      <=  5;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  1;
                              end
                     4'b0101: begin			// MOV direct, #imm8
                                itype      <=  10;
                                last_cycle <=  2;
                                src        <=  5;
                                src_cycle  <=  2;
                                dest       <=  8;
                              end
                     4'b0110,				// MOV @R0,#imm8
		     4'b0111: begin			// MOV @R1,#imm8
                                itype      <=  5;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  4;
                              end
                     default: begin			// MOV [R0..R7],#imm8
                                itype      <=  5;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  2;
                              end
                   endcase
                 end
        4'b1000: begin
                   case (op[3:0])
                     4'b0000: begin			// SJMP addr8
                                itype      <=  16;
                                last_cycle <=  2;
                              end
                     4'b0001: begin			// AJMP addr11
                                itype      <=  15;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// ANL C, direct_bit
                                itype      <=  6;
                                src        <=  7;
                                src_cycle  <=  1;
                                alu_op     <= `alu_op_anlcb;
                              end
                     4'b0011: begin			// MOVC A, @A+PC
                                itype      <=  19;
                                last_cycle <=  2;
                                src        <=  14;
                                src_cycle  <=  1;
                                dest       <=  5;
                              end
                     4'b0100: begin			// DIV AB
                                itype      <=  29;
                                last_cycle <=  4;
                                alu_op     <= `alu_op_div;
                              end
                     4'b0101: begin			// MOV direct,direct
                                itype      <=  9;
                                last_cycle <=  2;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  3;
                              end
                     4'b0110,				// MOV direct, @R0
		     4'b0111: begin			// MOV direct, @R1
                                itype      <=  5;
                                src        <=  4;
                                dest       <=  3;
                              end
                     default: begin		    // MOV direct, [R0..R7]
                                itype      <=  5;
                                src        <=  2;
                                dest       <=  3;
                              end
                   endcase
                 end
        4'b1001: begin
                   case (op[3:0])
                     4'b0000: begin			// MOV DPTR, #imm16
                                itype      <=  20;
                                last_cycle <=  2;
                                dest       <=  13;
                              end
                     4'b0001: begin			// ACALL addr11
                                itype      <=  14;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// MOV direct_bit,C
                                itype      <=  5;
                                src        <=  7;
                                src_cycle  <=  1;
                                dest       <=  7;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_movbc;
                              end
                     4'b0011: begin			// MOVC A, @A+DPTR
                                itype      <=  19;
                                last_cycle <=  2;
                                src        <=  14;
                                src_cycle  <=  1;
                                dest       <=  5;
                              end
                     4'b0100: begin			// SUBB A, #imm8
                                itype      <=  4;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_subb;
                              end
                     4'b0101: begin			// SUBB A, direct
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_subb;
                              end
                     4'b0110,				// SUBB A, @R0
		     4'b0111: begin			// SUBB A, @R1
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  1;
                                alu_op     <= `alu_op_subb;
                                chg_flags  <= 1'b1;
                              end
                     default: begin			// SUBB A, [R0..R7]
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  1;
                                alu_op     <= `alu_op_subb;