dw8051_op_decoder.v

Verilog版的C51核(DW8051)

// 1100_011x    1       4       10      -       1/1     XCH     A,@Ri
// 1100_1xxx    1       2       9       -       1/1     XCH     A,Rn
//
// 1101_0000    7       12      3       -       2/2     POP     direct
// 1101_0001    14      -       -       -       2/3     ACALL   code addr
// 1101_0010    5       7       7       1       2/2     SETB    bit
// 1101_0011    1       -       -       -       1/1     SETB    C
// 1101_0100    1       1       1       -       1/1     DA      A
// 1101_0101    26      3       3       1       3/4     DJNZ    direct,rel
// 1101_011x    1       4       11      -       1/1     XCHD    A,@Ri
// 1101_1xxx    13      2       2       -       2/3     DJNZ    Rn,rel
//
// 1110_0000    8       15      5       -       1/2*    MOVX    A,@DPTR
// 1110_0001    15      -       -       -       2/3     AJMP    code addr
// 1110_001x    8       6       5       -       1/2*    MOVX    A,@Ri
// 1110_0100    1       1       1       -       1/1     CLR     A
// 1110_0101    5       3       1       -       2/2     MOV     A,direct
// 1110_011x    1       4       1       -       1/1     MOV     A,@Ri
// 1110_1xxx    1       2       1       -       1/1     MOV     A,Rn
//
// 1111_0000    8       -       15      -       1/2*    MOVX    @DPTR,A
// 1111_0001    14      -       -       -       2/3     ACALL   code addr
// 1111_001x    8       8       6       -       1/2*    MOVX    @Ri,A
// 1111_0100    1       1       1       -       1/1     CPL     A
// 1111_0101    5       1       3       -       2/2     MOV     direct,A
// 1111_011x    1       1       4       -       1/1     MOV     @Ri,A
// 1111_1xxx    1       1       2       -       1/1     MOV     Rn,A
//
//
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
wire [7:0] op;
wire int;
wire idle_mode_n;
reg  [4:0] itype;            // 0..31
reg  [2:0] last_cycle;       // 0..7
reg  [3:0] src;              // 0..15
reg  [1:0] src_cycle;        // 0..3
reg  [3:0] dest;             // 0..15
reg  [5:0] alu_op;
reg  chg_flags;
reg  rmw;

//---------------
// local signals:
//---------------
//------------------------------------------------------------------------------

  always @(op or int or idle_mode_n)
  begin : dec_proc

    last_cycle <= 1;
    src        <= 0;
    src_cycle  <= 0;
    dest       <= 0;
    alu_op     <= `alu_op_trans;
    chg_flags  <= 0;
    rmw        <= 0;
    if (int == 1)
    begin 
      itype      <=  27;
      last_cycle <=  3;
    end
    else if (idle_mode_n == 0)
    begin 
      itype      <= 2;
      last_cycle <= 0;
    end
    else
    begin
      case (op[7:4])
        4'b0000: begin
                   case (op[3:0])
                     4'b0000: begin			// NOP
                                itype      <=  0;
                                last_cycle <=  0;
                              end
                     4'b0001: begin			// AJMP addr11
                                itype      <=  15;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// LJMP addr16
                                itype      <=  24;
                                last_cycle <=  3;
                              end
                     4'b0011: begin			// RR A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_rr;
                              end
                     4'b0100: begin			// INC A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_inc;
                              end
                     4'b0101: begin			// INC direct
                                itype      <=  5;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  3;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_inc;
                              end
                     4'b0110,				// INC @R0
                     4'b0111: begin			// INC @R1
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  4;
                                alu_op     <= `alu_op_inc;
                              end
                     default: begin			// INC [R0,R1...R7]
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  2;
                                alu_op     <= `alu_op_inc;
                              end
                   endcase
                 end
        4'b0001: begin
                   case (op[3:0])
                     4'b0000: begin			// JBC direct, rel
                                itype      <=  21;
                                last_cycle <=  3;
                                src        <=  7;
                                src_cycle  <=  1;
                                dest       <=  7;
                                alu_op     <= `alu_op_clrb;
                                rmw        <= 1'b1;
                              end
                     4'b0001: begin			// ACALL addr11
                                itype      <=  14;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// LCALL addr16
                                itype      <=  23;
                                last_cycle <=  3;
                              end
                     4'b0011: begin			// RRC A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_rrc;
                                chg_flags  <= 1'b1;
                              end
                     4'b0100: begin			// DEC A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_dec;
                              end
                     4'b0101: begin			// DEC direct
                                itype      <=  5;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  3;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_dec;
                              end
                     4'b0110,				// DEC @R0
                     4'b0111: begin			// DEC @R1
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  4;
                                alu_op     <= `alu_op_dec;
                              end
                     default: begin			// DEC [R0,R1..R7]
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  2;
                                alu_op     <= `alu_op_dec;
                              end
                   endcase
                 end
        4'b0010: begin
                   case (op[3:0])
                     4'b0000: begin			// JB direct,rel
                                itype      <=  21;
                                last_cycle <=  3;
                                src        <=  7;
                                src_cycle  <=  1;
                              end
                     4'b0001: begin			// AJMP addr11
                                itype      <=  15;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// RET
                                itype      <=  25;
                                last_cycle <=  3;
                              end
                     4'b0011: begin			//RL A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_rl;
                              end
                     4'b0100: begin			// ADD A, #imm8
                                itype      <=  4;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_add;
                              end
                     4'b0101: begin			//ADD A, direct
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_add;
                              end
                     4'b0110,				// ADD A, @R0
		     4'b0111: begin			// ADD A, @R1
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  1;
                                alu_op     <= `alu_op_add;
                                chg_flags  <= 1'b1;
                              end
                     default: begin			// ADD A, [R0,R1..R7]
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  1;
                                alu_op     <= `alu_op_add;
                                chg_flags  <= 1'b1;
                              end
                   endcase
                 end
        4'b0011: begin
                   case (op[3:0])				// JNB direct, rel
                     4'b0000: begin
                                itype      <=  21;
                                last_cycle <=  3;
                                src        <=  7;
                                src_cycle  <=  1;
                              end
                     4'b0001: begin			// ACALL addr11
                                itype      <=  14;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// RETI
                                itype      <=  25;
                                last_cycle <=  3;
                              end
                     4'b0011: begin			// ADDC A, #imm8
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_rlc;
                                chg_flags  <= 1'b1;
                              end
                     4'b0100: begin			// ADDC A, direct
                                itype      <=  4;
                                src        <=  5;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_addc;
                              end
                     4'b0101: begin			// RLC A
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_addc;
                              end
                     4'b0110,				// ADDC A, @R0
		     4'b0111: begin			// ADDC A, @R1
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  1;
                                alu_op     <= `alu_op_addc;
                                chg_flags  <= 1'b1;
                              end
                     default: begin			// ADDC A, [R0,R1..R7]
                                itype      <=  3;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  1;
                                alu_op     <= `alu_op_addc;
                                chg_flags  <= 1'b1;
                              end
                   endcase
                 end
        4'b0100: begin
                   case (op[3:0])
                     4'b0000: begin			// JC rel
                                itype      <=  18;
                                last_cycle <=  2;
                              end
                     4'b0001: begin			// AJMP addr11
                                itype      <=  15;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// ORL direct, A
                                itype      <=  4;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  3;