dw8051_cpu.v

Verilog版的C51核(DW8051)

// $Id: DW8051_cpu.v,v 1.1 1996/07/25 17:42:42 gina Exp $
//------------------------------------------------------------------------------
//
//        This confidential and proprietary software may be used only
//     as authorized by a licensing agreement from Synopsys Inc.
//     In the event of publication, the following notice is applicable:
//
//                    (C) COPYRIGHT 1996   SYNOPSYS INC.
//                          ALL RIGHTS RESERVED
//
//        The entire notice above must be reproduced on all authorized
//        copies.
//
// FILE: DW8051_cpu.v
//
// AUTHOR: Ludwig Rieder
//
// ABSTRACT: DW8051 main cpu module (Verilog version)
//
// MODIFICATION HISTORY:
//      L.Rieder        28.05.96        Verilog version created
//	L.Rieder	17.07.96	upper RAM returns FF if not existing
//
//      Gina Ngo        11.20.96        Fixed star 38722: added header
//	Bala Needmanglam
//			May 20,98	Changed all GTECH instantiations to HDL.
//                      July 20,1999    Removed all DesignWare-Foundation 
//                                      license checkout commands.
//------------------------------------------------------------------------------


`include "./DW8051/DW8051_package.inc"
`include "./DW8051/DW8051_parameter.v"

module DW8051_cpu (clk,
		   por_n,
                   rst_in_n,
                   rst_out_n,
                   test_mode_n,
                   cycle,
                   stop_mode_n,
                   idle_mode_n,

                   // sfr bus:
                   int_sfr_addr,
                   int_sfr_data_out,
                   int_sfr_data_in,
                   int_sfr_wr,
                   int_sfr_cs,
                   ext_sfr_addr,
                   ext_sfr_data_out,
    
                   ext_sfr_data_in,
                   ext_sfr_wr,
                   ext_sfr_rd,

                   // ext. memory interface
                   mem_addr,
                   mem_data_out,
                   mem_data_in,
                   mem_wr_n,
                   mem_rd_n,
                   mem_pswr_n,
                   mem_psrd_n,
                   mem_ale,
                   mem_ea_n,

                   // port control lines:
                   port_pin_reg_n,
                   p0_mem_reg_n,
                   p0_addr_data_n,
                   p2_mem_reg_n,
    
		   // Internal RAM interface (128 or 256 bytes):
		   iram_addr,
		   iram_data_out,
		   iram_data_in,
		   iram_rd_n,
		   iram_we1_n,
		   iram_we2_n,

                   // signals to serial:
                   smod,

                   // signals to timer:
                   tm,

                   // signals from/to DW8051_intr:
                   int_req,
                   int_src,
                   int_ack,
                   int_clr,

                   // internal ROM interface:
                   int_rom_data_in,
                   int_rom_rd_n,
                   int_rom_cs_n
		   );

parameter ram_256 = 0;		// 0: 128 Byte,     1: 256 Byte
parameter rom_addr_size = 0;	// 0..16 (0..64kB)
parameter extd_intr = 1;	// 0: std interrupt unit ( 7 interrupts)
				// 1: extended intr unit (13 interrupts)
 input clk;
 input por_n;
 input rst_in_n;
 input test_mode_n;
 input [7:0] int_sfr_data_in;
 input int_sfr_cs;
 input [7:0] ext_sfr_data_in;
 input [7:0] mem_data_in;
 input mem_ea_n;
 input int_req;
 input [3:0] int_src;
 input [7:0] iram_data_out;
 input [7:0] int_rom_data_in;
 output rst_out_n;
 output [1:0] cycle;
 output stop_mode_n;
 output idle_mode_n;
 output [7:0] int_sfr_addr;
 output [7:0] int_sfr_data_out;
 output int_sfr_wr;
 output [7:0] ext_sfr_addr;
 output [7:0] ext_sfr_data_out;
 output ext_sfr_wr;
 output ext_sfr_rd;
 output [15:0] mem_addr;
 output [7:0]  mem_data_out;
 output mem_wr_n;
 output mem_rd_n;
 output mem_pswr_n;
 output mem_psrd_n;
 output mem_ale;
 output port_pin_reg_n;
 output p0_mem_reg_n;
 output p0_addr_data_n;
 output p2_mem_reg_n;
 output [7:0] iram_addr;
 output [7:0] iram_data_in;
 output iram_rd_n;
 output iram_we1_n;
 output iram_we2_n;
 output smod;
 output [2:0] tm;
 output int_ack;
 output int_clr;
 output int_rom_rd_n;
 output int_rom_cs_n;

//------------------------------------------------------------------------------
//                             DESCRIPTION
//------------------------------------------------------------------------------
//
// Interrupts:
//            |c1|c2|c3|c4|c1|c2|c3|c4| ... |c1|c2|c3|c4|
// int_req  __xxxxxxxxxxxxx------xxxxxx     xxxxxxxxxxxxx
// int_ack  _____________________---___     _____________
// int_clr  ___________________________     _------------_  (RETI)
//
//------------------------------------------------------------------------------
wire clk;
wire por_n;
wire rst_in_n;
wire test_mode_n;
wire [7:0] int_sfr_data_in;
wire int_sfr_cs;
wire [7:0] ext_sfr_data_in;
wire [7:0] mem_data_in;
wire mem_ea_n;
wire int_req;
wire [3:0] int_src;
wire [7:0] int_rom_data_in;
wire rst_out_n;
wire [1:0] cycle;
wire stop_mode_n;
wire idle_mode_n;
wire [7:0] int_sfr_addr;
wire [7:0] int_sfr_data_out;
wire int_sfr_wr;
wire [7:0] ext_sfr_addr;
wire [7:0] ext_sfr_data_out;
wire ext_sfr_wr;
wire ext_sfr_rd;
wire [15:0] mem_addr;
wire [7:0] mem_data_out;
wire mem_wr_n;
wire mem_rd_n;
wire mem_pswr_n;
wire mem_psrd_n;
wire mem_ale;
wire port_pin_reg_n;
wire p0_mem_reg_n;
wire p0_addr_data_n;
wire p2_mem_reg_n;
wire [7:0] iram_addr;
wire [7:0] iram_data_in;
wire iram_rd_n;
wire iram_we1_n;
wire iram_we2_n;
wire smod;
wire [2:0] tm;
wire int_ack;
wire int_clr;
wire int_rom_rd_n;
wire int_rom_cs_n;


//---------------
// local signals:
//---------------
wire clk_n;
wire rst_n;
reg  por_n_del1;
reg  por_n_del2;
wire sync_por_n;
reg  old_rst_in_n;
reg  rst_first;
reg  sync_rst_n;
 
wire t_idle_mode_n;
wire t_stop_mode_n;
 
wire [7:0] ram_addr;
wire ram128_wr_addr_val_n;
wire ram256_wr_addr_val_n;
 
wire [7:0] ram_data_in;
wire ram128_wr_n;
wire ram256_wr_n;
wire ram_rd_n;
wire [7:0] t_sfr_addr;
wire [7:0] t_sfr_data_out;
wire [7:0] t_sfr_data_in;
wire t_sfr_wr;
wire [7:0] cpu_data_in;
wire cpu_sfr_cs;
wire [7:0] indir_data_in;
 
wire int_rec;
wire eie_eip_check;
 
// op_decoder signals:
wire [4:0] dec_itype;		// 0..31
wire [2:0] dec_last_cycle;	// 0..7
wire [3:0] dec_src;		// 0..15
wire [1:0] dec_src_cycle;	// 0..3
wire [3:0] dec_dest;		// 0.15
wire [5:0] dec_alu_op;
wire dec_chg_flags;
wire dec_rmw;
 
// cycle counter signals:
wire [1:0] t_cycle;
wire [1:0] t_cycle_n;		// dummy
 
// register:
wire [7:0] alu;
wire [7:0] alu_l;
wire [7:0] temp1;
wire [7:0] temp2;
wire [7:0] temp3;
wire [7:0] sp;			// Stack pointer
wire [7:0] dps;			// Data pointer sel
wire [7:0] pcon;		// Power control
wire [7:0] ckcon;		// Clock control
wire [7:0] psw;			// Prog.Stat.Word
wire [7:0] acc;			// Accumulator
wire [7:0] acc_data;
wire ld_acc;
wire ld_acc_direct;
wire [7:0] b;			// B register
wire [7:0] spc_fnc;		// SPC_FNC register
wire [7:0] sfr_reg_data_out;
wire sfr_reg_cs;
wire [7:0] mpage;
 
// lower/upper ram interface signals:
wire ram128_cs_n;
wire [7:0] ram128_data_out;
wire ram256_cs_n;
 
// pc signals:
wire [15:0] pc;
wire pc_tercnt;			// dummy
wire [15:0] result;		// res of execution
wire pc_cnt_dir;		// pc count direction
wire inc_pc;			// pc count enable
wire set_pc_n;
wire [7:0] pc_inc;		// pc increment
wire [7:0] pc_inc_h;
wire [15:0] pc_add;
wire pc_add_signed;
 
// 16 bit adder signals:
wire [15:0] add16_a;
wire [15:0] add16_b;
wire [15:0] add16_sum;
wire add16_co;			// dummy
wire sel_pc_dptr_n;
 
// dptr signals:
wire [15:0] dptr;
wire [7:0] dp_inc;		// dp increment
wire [15:0] dp_add;
 
// sp signals:
wire sp_cnt_dir;
wire cnt_sp;
 
// alu signals:
wire alu_co;
wire alu_aco;
wire alu_ovo;
wire [5:0] alu_op;
wire alu_zero;
wire alu_equal;
wire chg_flags;
 
// signals for bit operations:
wire bit_status;
wire [7:0] bit_nr;
 
// biu interface signals:
wire biu_wrs;
wire [15:0] biu_rom_addr;
wire [7:0] biu_instr;
wire [15:0] biu_ram_addr;
wire biu_wr_ram_addr_h;
wire biu_wr_ram_addr_l;
wire [7:0] biu_data_out;
wire biu_wr_ram;
wire biu_rd_ram;
wire biu_rd_rom;
wire [7:0] biu_data_in;
wire biu_ram_access_rdy;
wire [2:0] biu_md;
 

wire zero;
//------------------------------------------------------------------------------

  assign zero = 0;

  // if extended interrupt unit is present,
  // check for accesses to EIE and EIP:
  assign eie_eip_check = (extd_intr == 1) ? 1 : 0;


  //--------------------
  // Bus Interface Unit:
  //--------------------
  DW8051_biu #(rom_addr_size) i_biu
             (.clk             (clk),
              .rst_n           (rst_n),
              .cycle           (t_cycle),
              .ea_n            (mem_ea_n),
              .stop_mode_n     (t_stop_mode_n),
              .idle_mode_n     (t_idle_mode_n),
              .md              (biu_md),
              .wrs             (biu_wrs),
              .rom_addr        (biu_rom_addr),
              .instr_reg       (biu_instr),
              .ram_addr        (biu_ram_addr),
              .wr_ram_addr_h   (biu_wr_ram_addr_h),
              .wr_ram_addr_l   (biu_wr_ram_addr_l),
              .data_out        (biu_data_out),
              .wr_ram          (biu_wr_ram),
              .rd_ram          (biu_rd_ram),
              .rd_rom          (biu_rd_rom),
              .data_in         (biu_data_in),
              .ram_access_rdy  (biu_ram_access_rdy),
              .mem_addr        (mem_addr),
              .mem_data_out    (mem_data_out),
              .mem_data_in     (mem_data_in),
              .mem_wr_n        (mem_wr_n),
              .mem_rd_n        (mem_rd_n),
              .mem_pswr_n      (mem_pswr_n),