dw8051_intr_1.v

Verilog版的C51核(DW8051)

// $Id: DW8051_intr_1.v,v 1.1 1996/07/25 17:43:01 gina Exp $
//------------------------------------------------------------------------------
//
//        This confidential and proprietary software may be used only
//     as authorized by a licensing agreement from synopsys Inc.
//     In the event of publication, the following notice is applicable:
//
//                    (C) COPYRIGHT 1996   SYNOPSYS INC.
//                          ALL RIGHTS RESERVED
//
//        The entire notice above must be reproduced on all authorized
//        copies.
//
// FILE: DW8051_intr_1.v
//
// AUTHOR: Ludwig Rieder
//
// ABSTRACT: DW8051 interrupt module for 13 interrupt sources (extended)
//           (Verilog version)
//
// MODIFICATION HISTORY:
//      L.Rieder        28.05.96        Verilog version created
//
//      Bala Needamangalam
//                      Sep 15.98       Fix for STAR 58773: DW8051 Extended
//                                      Interrupt Unit malfuctions with Timer
//                                      0/1 interrupts and read-modify-write
//                                      instructions:
//                                      Changed the qualification for tf0_clr
//					and tf1_clr to "ack_l", instead of
//					"int_ack".
//                      July 20,1999    Removed all DesignWare-Foundation 
//                                      license checkout commands.
//------------------------------------------------------------------------------



`include "./DW8051/DW8051_package.inc"
`include "./DW8051/DW8051_parameter.v"


module DW8051_intr_1 (clk,
		      rst_n,

                      // sfr bus signals:
                      sfr_addr,
                      intr_sfr_cs,
                      intr_data_out,
                      intr_data_in,
                      sfr_wr,
    
                      // signals from/to DW8051_cpu:
                      cycle,
                      int_req,
                      int_src,
                      int_ack,
                      int_clr,

                      // interrupt source signals:
                      int0_n,		// ext int 0
                      int1_n,		// ext int 1
                      int2,		// ext int 2
                      int3_n,		// ext int 3
                      int4,		// ext int 4
                      int5_n,		// ext int 5
                      tf0_set,		// timer 0 int
                      tf1_set,		// timer 1 int
                      ri0,		// serial port 0 receive  int
                      ti0,		// serial port 0 transmit int
                      ri1,		// serial port 1 receive  int
                      ti1,		// serial port 1 transmit int
                      tf2,		// timer 2 int
                      exf2,		// ext timer 2 int
                      pfi,		// power fail int
                      wdti,		// watchdog timeout int

                      // signals to timer module
                      ena_t0,
                      ena_t1,

                      // signal to serial port 1 module
                      smod1
		      );
 input clk;
 input rst_n;
 input [7:0]  sfr_addr;
 input [7:0]  intr_data_in;
 input sfr_wr;
 input [1:0]  cycle;
 input int_ack;
 input int_clr;
 input int0_n;
 input int1_n;
 input int2;
 input int3_n;
 input int4;
 input int5_n;
 input tf0_set;
 input tf1_set;
 input ri0;
 input ti0;
 input ri1;
 input ti1;
 input tf2;
 input exf2;
 input pfi;
 input wdti;
 output intr_sfr_cs;
 output [7:0]  intr_data_out;
 output int_req;
 output [3:0]  int_src;
 output ena_t0;
 output ena_t1;
 output smod1;

//------------------------------------------------------------------------------
 wire clk;
 wire rst_n;
 wire [7:0] sfr_addr;
 wire [7:0] intr_data_in;
 wire sfr_wr;
 wire [1:0] cycle;
 wire int_ack;
 wire int_clr;
 wire int0_n;
 wire int1_n;
 wire int2;
 wire int3_n;
 wire int4;
 wire int5_n;
 wire tf0_set;
 wire tf1_set;
 wire ri0;
 wire ti0;
 wire ri1;
 wire ti1;
 wire tf2;
 wire exf2;
 wire pfi;
 wire wdti;
 wire intr_sfr_cs;
 wire [7:0] intr_data_out;
 wire int_req;
 wire [3:0] int_src;
 wire ena_t0;
 wire ena_t1;
 wire smod1;


//---------------
// local signals:
//---------------
reg  [7:0] ie_reg;		// ie register
wire ea;
wire et0;
wire et1;
wire et2;
wire es0;
wire es1;
wire ex0;
wire ex1;
 
reg  [6:0] ip_reg;		// ip register
wire pt0;
wire pt1;
wire pt2;
wire ps0;
wire ps1;
wire px0;
wire px1;
 
wire [7:0] tcon_reg;		// tcon register
reg  tf1;
reg  tr1;
reg  tf0;
reg  tr0;
reg  ie1;
reg  it1;
reg  ie0;
reg  it0;
 
reg  [7:4] exif_reg;		// exif register
wire ie2;
wire ie3;
wire ie4;
wire ie5;
 
reg  [4:0] eie_reg;		// eie register
wire ewdi;
wire ex5;
wire ex4;
wire ex3;
wire ex2;
 
reg  [4:0] eip_reg;		// eip register
wire pwdi;
wire px5;
wire px4;
wire px3;
wire px2;
 
wire [7:0] eicon_reg;		// eicon register
 
reg  smod1_reg;
reg  epfi;
reg  pfi_reg;
reg  wdti_reg;
 
wire wdti_set;
wire pfi_set;
 
wire ie_cs;			// chip select for ie-register
wire ip_cs;			// chip select for ip-register
wire tcon_cs;			// chip select for tcon-register
wire exif_cs;			// chip_select for exif-register
wire eie_cs;			// chip_select for eie-register
wire eip_cs;			// chip_select for eip-register
wire eicon_cs;			// chip_select for eicon_register
				// (includes: smod1reg, epfi, pfi_reg and
				// wdti_reg)
wire eicon_wr;
wire tcon_wr;
 
wire tf0_clr;
wire tf1_clr;
wire ie0_clr;
wire ie1_clr;
 
wire ie0_set;
wire ie1_set;
wire ie2_set;
wire ie3_set;
wire ie4_set;
wire ie5_set;
 
wire it0_set;
wire it1_set;
 
wire it0_clr;
wire it1_clr;
 
reg  ack_l;			// latched int_ack
 
reg  x0_l1_n;			// latched external interrupt 0
reg  x1_l1_n;			// latched external interrupt 1
reg  x2_l1;			// latched external interrupt 2
reg  x3_l1_n;			// latched external interrupt 3
reg  x4_l1;			// latched external interrupt 4
reg  x5_l1_n;			// latched external interrupt 5
 
reg  x0_l2_n;			// latched x0_l1_n
reg  x1_l2_n;			// latched x1_l1_n
reg  x2_l2;			// latched x2_l1
reg  x3_l2_n;			// latched x3_l1_n
reg  x4_l2;			// latched x4_l1
reg  x5_l2_n;			// latched x5_l1_n
 
reg  x0_l3_n;			// latched x0_l2_n
reg  x1_l3_n;			// latched x1_l2_n
reg  x2_l3;			// latched x2_l2
reg  x3_l3_n;			// latched x3_l2_n
reg  x4_l3;			// latched x4_l2
reg  x5_l3_n;			// latched x5_l2_n
 
reg  pfi_l1;			// latched pfi
reg  pfi_l2;			// latched pfi_l1
 
reg  wdti_l1;			// latched wdti
reg  wdti_l2;			// latched wdti_l1
reg  wdti_l3;			// latched wdti_l2
 
wire x0_req;			// request from int0
wire x1_req;			// request from int1
wire x2_req;			// request from int2
wire x3_req;			// request from int3
wire x4_req;			// request from int4
wire x5_req;			// request from int5
wire t0_req;			// request from timer0
wire t1_req;			// request from timer1
wire t2_req;			// request from timer2
wire s0_req;			// request from serial port 0
wire s1_req;			// request from serial port 1
wire wd_req;			// request from watchdog timer
wire pf_req;			// request from power fail detector
 
wire x0_hp_req;			// high priority request from int0
wire x1_hp_req;			// high priority request from int1
wire x2_hp_req;			// high priority request from int2
wire x3_hp_req;			// high priority request from int3
wire x4_hp_req;			// high priority request from int4
wire x5_hp_req;			// high priority request from int5
wire t0_hp_req;			// high priority request from timer0
wire t1_hp_req;			// high priority request from timer1
wire t2_hp_req;			// high priority request from timer2
wire s0_hp_req;			// high priority request from serial port0
wire s1_hp_req;			// high priority request from serial port1
wire wd_hp_req;			// high priority request from watchdog timer
 
wire x0_lp_req;			// low priority request from int0
wire x1_lp_req;			// low priority request from int1
wire x2_lp_req;			// low priority request from int2
wire x3_lp_req;			// low priority request from int3
wire x4_lp_req;			// low priority request from int4
wire x5_lp_req;			// low priority request from int5
wire t0_lp_req;			// low priority request from timer0
wire t1_lp_req;			// low priority request from timer1
wire t2_lp_req;			// low priority request from timer2
wire s0_lp_req;			// low priority request from serial port0
wire s1_lp_req;			// low priority request from serial port1
wire wd_lp_req;			// low priority request from watchdog timer
 
wire [3:0] lp_src;		// source for low  priority requ.
wire [3:0] hp_src;		// source for high priority requ.
wire [3:0] i_src;		// source for active request
reg  [3:0] i_src_l;		// latched i_src
 
reg  iip0;			// low  priority interrupt in progress flag
reg  iip1;			// high priority interrupt in progress flag
reg  iip2;			// power fail interrupt in progress
wire iip0_set;
wire iip1_set;
wire iip2_set;
wire iip0_clr;
wire iip1_clr;
wire iip2_clr;
 
reg  pf_req_l;			// latched highest priority request
                                // (from power fail detector)
wire hp_req;			// high priority request
wire lp_req;			// low  priority request
reg  hp_req_l;			// latched high priority request
reg  lp_req_l;			// latched low  priority request
 
// define interrupt source := interrupt_vector(6 downto 3)
`define  x0_src 4'b0000		// vector: 03h
`define  x1_src 4'b0010		// vector: 13h
`define  t0_src 4'b0001		// vector: 0Bh
`define  t1_src 4'b0011		// vector: 1Bh
`define  t2_src 4'b0101		// vector: 2Bh
`define  s0_src 4'b0100		// vector: 23h
`define  s1_src 4'b0111		// vector: 3Bh
`define  pf_src 4'b0110		// vector: 33h
`define  x2_src 4'b1000		// vector: 43h
`define  x3_src 4'b1001		// vector: 4Bh
`define  x4_src 4'b1010		// vector: 53h
`define  x5_src 4'b1011		// vector: 5Bh
`define  wd_src 4'b1100		// vector: 63h
 

//------------------------------------------------------------------------------

  // SFR Address decode
  assign ie_cs    = (sfr_addr == `ie_addr)    ? 1 : 0;
  assign ip_cs    = (sfr_addr == `ip_addr)    ? 1 : 0;
  assign tcon_cs  = (sfr_addr == `tcon_addr)  ? 1 : 0;
  assign exif_cs  = (sfr_addr == `exif_addr)  ? 1 : 0;
  assign eie_cs   = (sfr_addr == `eie_addr)   ? 1 : 0;
  assign eip_cs   = (sfr_addr == `eip_addr)   ? 1 : 0;
  assign eicon_cs = (sfr_addr == `eicon_addr) ? 1 : 0;

  // Write-enables for EICON and TCON
  assign eicon_wr = sfr_wr & eicon_cs;
  assign tcon_wr  = sfr_wr & tcon_cs;

  // Software programming for IT0 set and clear
  assign it0_set  = tcon_wr &  intr_data_in[0];
  assign it0_clr  = tcon_wr & ~intr_data_in[0];

  // Software programming for IT1 set and clear
  assign it1_set  = tcon_wr &  intr_data_in[2];
  assign it1_clr  = tcon_wr & ~intr_data_in[2];

  // Defining the IE0 flag settings
  assign ie0_set  = (cycle != `c1) ? 0                    :
                    (it0_clr == 1) ?  ~x0_l2_n            : // Low-level sens.
                    (it0_set == 1) ? (~x0_l2_n & x0_l3_n) : // Fall-edge sens.
                    (it0     == 0) ?  ~x0_l2_n            : // Low-level sens.
                                     (~x0_l2_n & x0_l3_n);  // Fall-edge sens.
  // Defining the IE1 flag settings
  assign ie1_set  = (cycle != `c1) ? 0                    :
                    (it1_clr == 1) ?  ~x1_l2_n            : // Low-level sens.
                    (it1_set == 1) ? (~x1_l2_n & x1_l3_n) : // Fall-edge sens.
                    (it1     == 0) ?  ~x1_l2_n            : // Low-level sens.
                                     (~x1_l2_n & x1_l3_n);  // Fall-edge sens.

  // Defining the IE2 flag settings
  assign ie2_set  = (cycle != `c1) ? 0 : ( x2_l2   & ~x2_l3);   // rise edge

  // Defining the IE3 flag settings
  assign ie3_set  = (cycle != `c1) ? 0 : (~x3_l2_n &  x3_l3_n); // fall-edge

  // Defining the IE4 flag settings
  assign ie4_set  = (cycle != `c1) ? 0 : ( x4_l2   & ~x4_l3);   // rise edge

  // Defining the IE5 flag settings
  assign ie5_set  = (cycle != `c1) ? 0 : (~x5_l2_n &  x5_l3_n); // fall-edge

  assign ie0_clr  = (((ack_l & it0) == 1) & (i_src_l == `x0_src)) ? 1 :
  					// int-ack cycle
                    (cycle != `c1) ? 0       :
                    (it0_set == 1) ? 0       : // fall-edge sens & detected
                    (it0_clr == 1) ? x0_l2_n : // low-level sens & 1 detected
                    (it0     == 0) ? x0_l2_n : // low-level sens & 1 detected
                                     0;

  assign ie1_clr  = (((ack_l & it1) == 1) & (i_src_l == `x1_src)) ? 1 :
  					// int-ack cycle
                    (cycle != `c1) ? 0       :
                    (it1_set == 1) ? 0       : // fall-edge sens & detected
                    (it1_clr == 1) ? x1_l2_n : // low-level sens & 1 detected
                    (it1     == 0) ? x1_l2_n : // low-level sens & 1 detected
                                     0;

  assign tf0_clr  = ((ack_l == 1) & (i_src_l == `t0_src)) ? 1 : 0;
  		// TF0 flag is cleared in the int-ack cycle.

  assign tf1_clr  = ((ack_l == 1) & (i_src_l == `t1_src)) ? 1 : 0;
  		// TF1 flag is cleared in the int-ack cycle.

  assign pfi_set  = (cycle != `c1) ? 0 : pfi_l2;
  		// PFI is a level-sensitive interrupt.

  assign wdti_set = (cycle != `c1) ? 0 : (wdti_l2 & ~wdti_l3);
  		// WDTI is an edge-sensitive interrupt