usb1_core.v

USB 1.1的verilog代码

wire	[7:0]	ep0_dout;
wire		ep0_re, ep0_we;
wire	[13:0]	ep0_cfg;
wire	[7:0]	ep0_size;
wire	[7:0]	ep0_ctrl_dout, ep0_ctrl_din;
wire		ep0_ctrl_re, ep0_ctrl_we;
wire	[3:0]	ep0_ctrl_stat;

wire		ctrl_setup, ctrl_in, ctrl_out;
wire		send_stall;
wire		token_valid;
reg		rst_local;		// internal reset
wire		dropped_frame;
wire		misaligned_frame;
wire		v_set_int;
wire		v_set_feature;
wire	[15:0]	wValue;
wire	[15:0]	wIndex;

reg		ep_bf_en;
reg	[6:0]	ep_bf_size;
wire	[6:0]	rom_adr;
wire	[7:0]	rom_data;

///////////////////////////////////////////////////////////////////
//
// Misc Logic
//

// Endpoint type and Max transfer size
assign ep0_cfg = `CTRL | ep0_size;

always @(posedge clk_i)
	rst_local <= #1 rst_i & ~usb_rst;

///////////////////////////////////////////////////////////////////
//
// Module Instantiations
//

usb_phy phy(
		.clk(			clk_i			),
		.rst(			rst_i			),	// ONLY external reset
		.phy_tx_mode(		phy_tx_mode		),
		.usb_rst(		usb_rst			),

		// Transceiver Interface
		.rxd(			rx_d			),
		.rxdp(			rx_dp			),
		.rxdn(			rx_dn			),
		.txdp(			tx_dp			),
		.txdn(			tx_dn			),
		.txoe(			tx_oe			),

		// UTMI Interface
		.DataIn_o(		DataIn			),
		.RxValid_o(		RxValid			),
		.RxActive_o(		RxActive		),
		.RxError_o(		RxError			),
		.DataOut_i(		DataOut			),
		.TxValid_i(		TxValid			),
		.TxReady_o(		TxReady			),
		.LineState_o(		LineState		)
		);

// UTMI Interface
usb1_utmi_if	u0(
		.phy_clk(		clk_i			),
		.rst(			rst_local		),
		.DataOut(		DataOut			),
		.TxValid(		TxValid			),
		.TxReady(		TxReady			),
		.RxValid(		RxValid			),
		.RxActive(		RxActive		),
		.RxError(		RxError			),
		.DataIn(		DataIn			),
		.rx_data(		rx_data			),
		.rx_valid(		rx_valid		),
		.rx_active(		rx_active		),
		.rx_err(		rx_err			),
		.tx_data(		tx_data			),
		.tx_valid(		tx_valid		),
		.tx_valid_last(		tx_valid_last		),
		.tx_ready(		tx_ready		),
		.tx_first(		tx_first		)
		);

// Protocol Layer
usb1_pl  u1(	.clk(			clk_i			),
		.rst(			rst_local		),
		.rx_data(		rx_data			),
		.rx_valid(		rx_valid		),
		.rx_active(		rx_active		),
		.rx_err(		rx_err			),
		.tx_data(		tx_data			),
		.tx_valid(		tx_valid		),
		.tx_valid_last(		tx_valid_last		),
		.tx_ready(		tx_ready		),
		.tx_first(		tx_first		),
		.tx_valid_out(		TxValid			),
		.token_valid(		token_valid		),
		.fa(			funct_adr		),
		.ep_sel(		ep_sel			),
		.x_busy(		usb_busy		),
		.int_crc16_set(		crc16_err		),
		.int_to_set(		int_to_set		),
		.int_seqerr_set(	int_seqerr_set		),
		.frm_nat(		frm_nat			),
		.pid_cs_err(		pid_cs_err		),
		.nse_err(		nse_err			),
		.crc5_err(		crc5_err		),
		.rx_size(		rx_size			),
		.rx_done(		rx_done			),
		.ctrl_setup(		ctrl_setup		),
		.ctrl_in(		ctrl_in			),
		.ctrl_out(		ctrl_out		),
		.ep_bf_en(		ep_bf_en		),
		.ep_bf_size(		ep_bf_size		),
		.dropped_frame(		dropped_frame		),
		.misaligned_frame(	misaligned_frame	),
		.csr(			cfg			),
		.tx_data_st(		tx_data_st		),
		.rx_data_st(		rx_data_st		),
		.idma_re(		idma_re			),
		.idma_we(		idma_we			),
		.ep_empty(		ep_empty		),
		.ep_full(		ep_full			),
		.send_stall(		send_stall		)
		);

usb1_ctrl  u4(	.clk(			clk_i			),
		.rst(			rst_local		),

		.rom_adr(		rom_adr			),
		.rom_data(		rom_data		),

		.ctrl_setup(		ctrl_setup		),
		.ctrl_in(		ctrl_in			),
		.ctrl_out(		ctrl_out		),

		.ep0_din(		ep0_ctrl_dout		),
		.ep0_dout(		ep0_ctrl_din		),
		.ep0_re(		ep0_ctrl_re		),
		.ep0_we(		ep0_ctrl_we		),
		.ep0_stat(		ep0_ctrl_stat		),
		.ep0_size(		ep0_size		),

		.send_stall(		send_stall		),
		.frame_no(		frm_nat[26:16]		),
		.funct_adr(		funct_adr 		),
		.configured(					),
		.halt(						),

		.v_set_int(		v_set_int		),
		.v_set_feature(		v_set_feature		),
		.wValue(		wValue			),
		.wIndex(		wIndex			),
		.vendor_data(		vendor_data		)
		);


usb1_rom1 rom1(	.clk(		clk_i		),
		.adr(		rom_adr		),
		.dout(		rom_data	)
		);

// CTRL Endpoint FIFO
generic_fifo_sc_a #(8,6,0) u10(
		.clk(			clk_i			),
		.rst(			rst_i			),
		.clr(			usb_rst			),
		.din(			rx_data_st		),
		.we(			ep0_we			),
		.dout(			ep0_ctrl_dout		),
		.re(			ep0_ctrl_re		),
		.full_r(					),
		.empty_r(					),
		.full(			ep0_full		),
		.empty(			ep0_ctrl_stat[1]	),
		.full_n(					),
		.empty_n(					),
		.full_n_r(					),
		.empty_n_r(					),
		.level(						)
		);

generic_fifo_sc_a #(8,6,0) u11(
		.clk(			clk_i			),
		.rst(			rst_i			),
		.clr(			usb_rst			),
		.din(			ep0_ctrl_din		),
		.we(			ep0_ctrl_we		),
		.dout(			ep0_dout		),
		.re(			ep0_re			),
		.full_r(					),
		.empty_r(					),
		.full(			ep0_ctrl_stat[2]	),
		.empty(			ep0_empty		),
		.full_n(					),
		.empty_n(					),
		.full_n_r(					),
		.empty_n_r(					),
		.level(						)
		);

///////////////////////////////////////////////////////////////////
//
// Endpoint FIFO Interfaces
//

always @(ep_sel or ep0_cfg or ep1_cfg or ep2_cfg or ep3_cfg or
		ep4_cfg or ep5_cfg or ep6_cfg or ep7_cfg)
	case(ep_sel)	// synopsys full_case parallel_case
	   4'h0:	cfg = ep0_cfg;
	   4'h1:	cfg = ep1_cfg;
	   4'h2:	cfg = ep2_cfg;
	   4'h3:	cfg = ep3_cfg;
	   4'h4:	cfg = ep4_cfg;
	   4'h5:	cfg = ep5_cfg;
	   4'h6:	cfg = ep6_cfg;
	   4'h7:	cfg = ep7_cfg;
	endcase

// In endpoints only
always @(posedge clk_i)
	case(ep_sel)	// synopsys full_case parallel_case
	   4'h0:	tx_data_st <= #1 ep0_dout;
	   4'h1:	tx_data_st <= #1 ep1_din;
	   4'h2:	tx_data_st <= #1 ep2_din;
	   4'h3:	tx_data_st <= #1 ep3_din;
	   4'h4:	tx_data_st <= #1 ep4_din;
	   4'h5:	tx_data_st <= #1 ep5_din;
	   4'h6:	tx_data_st <= #1 ep6_din;
	   4'h7:	tx_data_st <= #1 ep7_din;
	endcase

// In endpoints only
always @(posedge clk_i)
	case(ep_sel)	// synopsys full_case parallel_case
	   4'h0:	ep_empty <= #1 ep0_empty;
	   4'h1:	ep_empty <= #1 ep1_empty;
	   4'h2:	ep_empty <= #1 ep2_empty;
	   4'h3:	ep_empty <= #1 ep3_empty;
	   4'h4:	ep_empty <= #1 ep4_empty;
	   4'h5:	ep_empty <= #1 ep5_empty;
	   4'h6:	ep_empty <= #1 ep6_empty;
	   4'h7:	ep_empty <= #1 ep7_empty;
	endcase

// OUT endpoints only
always @(ep_sel or ep0_full or ep1_full or ep2_full or ep3_full or
		ep4_full or ep5_full or ep6_full or ep7_full)
	case(ep_sel)	// synopsys full_case parallel_case
	   4'h0:	ep_full = ep0_full;
	   4'h1:	ep_full = ep1_full;
	   4'h2:	ep_full = ep2_full;
	   4'h3:	ep_full = ep3_full;
	   4'h4:	ep_full = ep4_full;
	   4'h5:	ep_full = ep5_full;
	   4'h6:	ep_full = ep6_full;
	   4'h7:	ep_full = ep7_full;
	endcase

always @(posedge clk_i)
	case(ep_sel)	// synopsys full_case parallel_case
	   4'h0:	ep_bf_en = 1'b0;
	   4'h1:	ep_bf_en = ep1_bf_en;
	   4'h2:	ep_bf_en = ep2_bf_en;
	   4'h3:	ep_bf_en = ep3_bf_en;
	   4'h4:	ep_bf_en = ep4_bf_en;
	   4'h5:	ep_bf_en = ep5_bf_en;
	   4'h6:	ep_bf_en = ep6_bf_en;
	   4'h7:	ep_bf_en = ep7_bf_en;
	endcase

always @(posedge clk_i)
	case(ep_sel)	// synopsys full_case parallel_case
	   4'h1:	ep_bf_size = ep1_bf_size;
	   4'h2:	ep_bf_size = ep2_bf_size;
	   4'h3:	ep_bf_size = ep3_bf_size;
	   4'h4:	ep_bf_size = ep4_bf_size;
	   4'h5:	ep_bf_size = ep5_bf_size;
	   4'h6:	ep_bf_size = ep6_bf_size;
	   4'h7:	ep_bf_size = ep7_bf_size;
	endcase

assign ep1_dout = rx_data_st;
assign ep2_dout = rx_data_st;
assign ep3_dout = rx_data_st;
assign ep4_dout = rx_data_st;
assign ep5_dout = rx_data_st;
assign ep6_dout = rx_data_st;
assign ep7_dout = rx_data_st;

assign ep0_re = idma_re & (ep_sel == 4'h00);
assign ep1_re = idma_re & (ep_sel == 4'h01) & !ep1_empty;
assign ep2_re = idma_re & (ep_sel == 4'h02) & !ep2_empty;
assign ep3_re = idma_re & (ep_sel == 4'h03) & !ep3_empty;
assign ep4_re = idma_re & (ep_sel == 4'h04) & !ep4_empty;
assign ep5_re = idma_re & (ep_sel == 4'h05) & !ep5_empty;
assign ep6_re = idma_re & (ep_sel == 4'h06) & !ep6_empty;
assign ep7_re = idma_re & (ep_sel == 4'h07) & !ep7_empty;

assign ep0_we = idma_we & (ep_sel == 4'h00);
assign ep1_we = idma_we & (ep_sel == 4'h01) & !ep1_full;
assign ep2_we = idma_we & (ep_sel == 4'h02) & !ep2_full;
assign ep3_we = idma_we & (ep_sel == 4'h03) & !ep3_full;
assign ep4_we = idma_we & (ep_sel == 4'h04) & !ep4_full;
assign ep5_we = idma_we & (ep_sel == 4'h05) & !ep5_full;
assign ep6_we = idma_we & (ep_sel == 4'h06) & !ep6_full;
assign ep7_we = idma_we & (ep_sel == 4'h07) & !ep7_full;

endmodule