de2_ccd_pip.hier_info

altera de2 开发板 vga lcd控制quatus 工程

address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[0] => ram_block3a10.PORTAADDR
address_a[0] => ram_block3a11.PORTAADDR
address_a[0] => ram_block3a12.PORTAADDR
address_a[0] => ram_block3a13.PORTAADDR
address_a[0] => ram_block3a14.PORTAADDR
address_a[0] => ram_block3a15.PORTAADDR
address_a[0] => ram_block3a16.PORTAADDR
address_a[0] => ram_block3a17.PORTAADDR
address_a[0] => ram_block3a18.PORTAADDR
address_a[0] => ram_block3a19.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[1] => ram_block3a10.PORTAADDR1
address_a[1] => ram_block3a11.PORTAADDR1
address_a[1] => ram_block3a12.PORTAADDR1
address_a[1] => ram_block3a13.PORTAADDR1
address_a[1] => ram_block3a14.PORTAADDR1
address_a[1] => ram_block3a15.PORTAADDR1
address_a[1] => ram_block3a16.PORTAADDR1
address_a[1] => ram_block3a17.PORTAADDR1
address_a[1] => ram_block3a18.PORTAADDR1
address_a[1] => ram_block3a19.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[2] => ram_block3a10.PORTAADDR2
address_a[2] => ram_block3a11.PORTAADDR2
address_a[2] => ram_block3a12.PORTAADDR2
address_a[2] => ram_block3a13.PORTAADDR2
address_a[2] => ram_block3a14.PORTAADDR2
address_a[2] => ram_block3a15.PORTAADDR2
address_a[2] => ram_block3a16.PORTAADDR2
address_a[2] => ram_block3a17.PORTAADDR2
address_a[2] => ram_block3a18.PORTAADDR2
address_a[2] => ram_block3a19.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[3] => ram_block3a10.PORTAADDR3
address_a[3] => ram_block3a11.PORTAADDR3
address_a[3] => ram_block3a12.PORTAADDR3
address_a[3] => ram_block3a13.PORTAADDR3
address_a[3] => ram_block3a14.PORTAADDR3
address_a[3] => ram_block3a15.PORTAADDR3
address_a[3] => ram_block3a16.PORTAADDR3
address_a[3] => ram_block3a17.PORTAADDR3
address_a[3] => ram_block3a18.PORTAADDR3
address_a[3] => ram_block3a19.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[4] => ram_block3a10.PORTAADDR4
address_a[4] => ram_block3a11.PORTAADDR4
address_a[4] => ram_block3a12.PORTAADDR4
address_a[4] => ram_block3a13.PORTAADDR4
address_a[4] => ram_block3a14.PORTAADDR4
address_a[4] => ram_block3a15.PORTAADDR4
address_a[4] => ram_block3a16.PORTAADDR4
address_a[4] => ram_block3a17.PORTAADDR4
address_a[4] => ram_block3a18.PORTAADDR4
address_a[4] => ram_block3a19.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[5] => ram_block3a8.PORTAADDR5
address_a[5] => ram_block3a9.PORTAADDR5
address_a[5] => ram_block3a10.PORTAADDR5
address_a[5] => ram_block3a11.PORTAADDR5
address_a[5] => ram_block3a12.PORTAADDR5
address_a[5] => ram_block3a13.PORTAADDR5
address_a[5] => ram_block3a14.PORTAADDR5
address_a[5] => ram_block3a15.PORTAADDR5
address_a[5] => ram_block3a16.PORTAADDR5
address_a[5] => ram_block3a17.PORTAADDR5
address_a[5] => ram_block3a18.PORTAADDR5
address_a[5] => ram_block3a19.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[6] => ram_block3a8.PORTAADDR6
address_a[6] => ram_block3a9.PORTAADDR6
address_a[6] => ram_block3a10.PORTAADDR6
address_a[6] => ram_block3a11.PORTAADDR6
address_a[6] => ram_block3a12.PORTAADDR6
address_a[6] => ram_block3a13.PORTAADDR6
address_a[6] => ram_block3a14.PORTAADDR6
address_a[6] => ram_block3a15.PORTAADDR6
address_a[6] => ram_block3a16.PORTAADDR6
address_a[6] => ram_block3a17.PORTAADDR6
address_a[6] => ram_block3a18.PORTAADDR6
address_a[6] => ram_block3a19.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[7] => ram_block3a8.PORTAADDR7
address_a[7] => ram_block3a9.PORTAADDR7
address_a[7] => ram_block3a10.PORTAADDR7
address_a[7] => ram_block3a11.PORTAADDR7
address_a[7] => ram_block3a12.PORTAADDR7
address_a[7] => ram_block3a13.PORTAADDR7
address_a[7] => ram_block3a14.PORTAADDR7
address_a[7] => ram_block3a15.PORTAADDR7
address_a[7] => ram_block3a16.PORTAADDR7
address_a[7] => ram_block3a17.PORTAADDR7
address_a[7] => ram_block3a18.PORTAADDR7
address_a[7] => ram_block3a19.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_a[8] => ram_block3a8.PORTAADDR8
address_a[8] => ram_block3a9.PORTAADDR8
address_a[8] => ram_block3a10.PORTAADDR8
address_a[8] => ram_block3a11.PORTAADDR8
address_a[8] => ram_block3a12.PORTAADDR8
address_a[8] => ram_block3a13.PORTAADDR8
address_a[8] => ram_block3a14.PORTAADDR8
address_a[8] => ram_block3a15.PORTAADDR8
address_a[8] => ram_block3a16.PORTAADDR8
address_a[8] => ram_block3a17.PORTAADDR8
address_a[8] => ram_block3a18.PORTAADDR8
address_a[8] => ram_block3a19.PORTAADDR8
address_a[9] => ram_block3a0.PORTAADDR9
address_a[9] => ram_block3a1.PORTAADDR9
address_a[9] => ram_block3a2.PORTAADDR9
address_a[9] => ram_block3a3.PORTAADDR9
address_a[9] => ram_block3a4.PORTAADDR9
address_a[9] => ram_block3a5.PORTAADDR9
address_a[9] => ram_block3a6.PORTAADDR9
address_a[9] => ram_block3a7.PORTAADDR9
address_a[9] => ram_block3a8.PORTAADDR9
address_a[9] => ram_block3a9.PORTAADDR9
address_a[9] => ram_block3a10.PORTAADDR9
address_a[9] => ram_block3a11.PORTAADDR9
address_a[9] => ram_block3a12.PORTAADDR9
address_a[9] => ram_block3a13.PORTAADDR9
address_a[9] => ram_block3a14.PORTAADDR9
address_a[9] => ram_block3a15.PORTAADDR9
address_a[9] => ram_block3a16.PORTAADDR9
address_a[9] => ram_block3a17.PORTAADDR9
address_a[9] => ram_block3a18.PORTAADDR9
address_a[9] => ram_block3a19.PORTAADDR9
address_a[10] => ram_block3a0.PORTAADDR10
address_a[10] => ram_block3a1.PORTAADDR10
address_a[10] => ram_block3a2.PORTAADDR10
address_a[10] => ram_block3a3.PORTAADDR10
address_a[10] => ram_block3a4.PORTAADDR10
address_a[10] => ram_block3a5.PORTAADDR10
address_a[10] => ram_block3a6.PORTAADDR10
address_a[10] => ram_block3a7.PORTAADDR10
address_a[10] => ram_block3a8.PORTAADDR10
address_a[10] => ram_block3a9.PORTAADDR10
address_a[10] => ram_block3a10.PORTAADDR10
address_a[10] => ram_block3a11.PORTAADDR10
address_a[10] => ram_block3a12.PORTAADDR10
address_a[10] => ram_block3a13.PORTAADDR10
address_a[10] => ram_block3a14.PORTAADDR10
address_a[10] => ram_block3a15.PORTAADDR10
address_a[10] => ram_block3a16.PORTAADDR10
address_a[10] => ram_block3a17.PORTAADDR10
address_a[10] => ram_block3a18.PORTAADDR10
address_a[10] => ram_block3a19.PORTAADDR10
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[0] => ram_block3a8.PORTBADDR
address_b[0] => ram_block3a9.PORTBADDR
address_b[0] => ram_block3a10.PORTBADDR
address_b[0] => ram_block3a11.PORTBADDR
address_b[0] => ram_block3a12.PORTBADDR
address_b[0] => ram_block3a13.PORTBADDR
address_b[0] => ram_block3a14.PORTBADDR
address_b[0] => ram_block3a15.PORTBADDR
address_b[0] => ram_block3a16.PORTBADDR
address_b[0] => ram_block3a17.PORTBADDR
address_b[0] => ram_block3a18.PORTBADDR
address_b[0] => ram_block3a19.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[1] => ram_block3a8.PORTBADDR1
address_b[1] => ram_block3a9.PORTBADDR1
address_b[1] => ram_block3a10.PORTBADDR1
address_b[1] => ram_block3a11.PORTBADDR1
address_b[1] => ram_block3a12.PORTBADDR1
address_b[1] => ram_block3a13.PORTBADDR1
address_b[1] => ram_block3a14.PORTBADDR1
address_b[1] => ram_block3a15.PORTBADDR1
address_b[1] => ram_block3a16.PORTBADDR1
address_b[1] => ram_block3a17.PORTBADDR1
address_b[1] => ram_block3a18.PORTBADDR1
address_b[1] => ram_block3a19.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[2] => ram_block3a8.PORTBADDR2
address_b[2] => ram_block3a9.PORTBADDR2
address_b[2] => ram_block3a10.PORTBADDR2
address_b[2] => ram_block3a11.PORTBADDR2
address_b[2] => ram_block3a12.PORTBADDR2
address_b[2] => ram_block3a13.PORTBADDR2
address_b[2] => ram_block3a14.PORTBADDR2
address_b[2] => ram_block3a15.PORTBADDR2
address_b[2] => ram_block3a16.PORTBADDR2
address_b[2] => ram_block3a17.PORTBADDR2
address_b[2] => ram_block3a18.PORTBADDR2
address_b[2] => ram_block3a19.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[3] => ram_block3a8.PORTBADDR3
address_b[3] => ram_block3a9.PORTBADDR3
address_b[3] => ram_block3a10.PORTBADDR3
address_b[3] => ram_block3a11.PORTBADDR3
address_b[3] => ram_block3a12.PORTBADDR3
address_b[3] => ram_block3a13.PORTBADDR3
address_b[3] => ram_block3a14.PORTBADDR3
address_b[3] => ram_block3a15.PORTBADDR3
address_b[3] => ram_block3a16.PORTBADDR3
address_b[3] => ram_block3a17.PORTBADDR3
address_b[3] => ram_block3a18.PORTBADDR3
address_b[3] => ram_block3a19.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[4] => ram_block3a8.PORTBADDR4
address_b[4] => ram_block3a9.PORTBADDR4
address_b[4] => ram_block3a10.PORTBADDR4
address_b[4] => ram_block3a11.PORTBADDR4
address_b[4] => ram_block3a12.PORTBADDR4
address_b[4] => ram_block3a13.PORTBADDR4
address_b[4] => ram_block3a14.PORTBADDR4
address_b[4] => ram_block3a15.PORTBADDR4
address_b[4] => ram_block3a16.PORTBADDR4
address_b[4] => ram_block3a17.PORTBADDR4
address_b[4] => ram_block3a18.PORTBADDR4
address_b[4] => ram_block3a19.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[5] => ram_block3a8.PORTBADDR5
address_b[5] => ram_block3a9.PORTBADDR5
address_b[5] => ram_block3a10.PORTBADDR5
address_b[5] => ram_block3a11.PORTBADDR5
address_b[5] => ram_block3a12.PORTBADDR5
address_b[5] => ram_block3a13.PORTBADDR5
address_b[5] => ram_block3a14.PORTBADDR5
address_b[5] => ram_block3a15.PORTBADDR5
address_b[5] => ram_block3a16.PORTBADDR5
address_b[5] => ram_block3a17.PORTBADDR5
address_b[5] => ram_block3a18.PORTBADDR5
address_b[5] => ram_block3a19.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[6] => ram_block3a8.PORTBADDR6
address_b[6] => ram_block3a9.PORTBADDR6
address_b[6] => ram_block3a10.PORTBADDR6
address_b[6] => ram_block3a11.PORTBADDR6
address_b[6] => ram_block3a12.PORTBADDR6
address_b[6] => ram_block3a13.PORTBADDR6
address_b[6] => ram_block3a14.PORTBADDR6
address_b[6] => ram_block3a15.PORTBADDR6
address_b[6] => ram_block3a16.PORTBADDR6
address_b[6] => ram_block3a17.PORTBADDR6
address_b[6] => ram_block3a18.PORTBADDR6
address_b[6] => ram_block3a19.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
address_b[7] => ram_block3a8.PORTBADDR7
address_b[7] => ram_block3a9.PORTBADDR7
address_b[7] => ram_block3a10.PORTBADDR7
address_b[7] => ram_block3a11.PORTBADDR7
address_b[7] => ram_block3a12.PORTBADDR7
address_b[7] => ram_block3a13.PORTBADDR7
address_b[7] => ram_block3a14.PORTBADDR7
address_b[7] => ram_block3a15.PORTBADDR7
address_b[7] => ram_block3a16.PORTBADDR7
address_b[7] => ram_