de2_ccd_pip.hier_info

altera de2 开发板 vga lcd控制quatus 工程

iCLK => Y_Cont[6].CLK
iCLK => Y_Cont[5].CLK
iCLK => Y_Cont[4].CLK
iCLK => Y_Cont[3].CLK
iCLK => Y_Cont[2].CLK
iCLK => Y_Cont[1].CLK
iCLK => Y_Cont[0].CLK
iCLK => Frame_Cont[31].CLK
iCLK => Frame_Cont[30].CLK
iCLK => Frame_Cont[29].CLK
iCLK => Frame_Cont[28].CLK
iCLK => Frame_Cont[27].CLK
iCLK => Frame_Cont[26].CLK
iCLK => Frame_Cont[25].CLK
iCLK => Frame_Cont[24].CLK
iCLK => Frame_Cont[23].CLK
iCLK => Frame_Cont[22].CLK
iCLK => Frame_Cont[21].CLK
iCLK => Frame_Cont[20].CLK
iCLK => Frame_Cont[19].CLK
iCLK => Frame_Cont[18].CLK
iCLK => Frame_Cont[17].CLK
iCLK => Frame_Cont[16].CLK
iCLK => Frame_Cont[15].CLK
iCLK => Frame_Cont[14].CLK
iCLK => Frame_Cont[13].CLK
iCLK => Frame_Cont[12].CLK
iCLK => Frame_Cont[11].CLK
iCLK => Frame_Cont[10].CLK
iCLK => Frame_Cont[9].CLK
iCLK => Frame_Cont[8].CLK
iCLK => Frame_Cont[7].CLK
iCLK => Frame_Cont[6].CLK
iCLK => Frame_Cont[5].CLK
iCLK => Frame_Cont[4].CLK
iCLK => Frame_Cont[3].CLK
iCLK => Frame_Cont[2].CLK
iCLK => Frame_Cont[1].CLK
iCLK => Frame_Cont[0].CLK
iRST => mSTART.ACLR
iRST => Frame_Cont[0].ACLR
iRST => Frame_Cont[1].ACLR
iRST => Frame_Cont[2].ACLR
iRST => Frame_Cont[3].ACLR
iRST => Frame_Cont[4].ACLR
iRST => Frame_Cont[5].ACLR
iRST => Frame_Cont[6].ACLR
iRST => Frame_Cont[7].ACLR
iRST => Frame_Cont[8].ACLR
iRST => Frame_Cont[9].ACLR
iRST => Frame_Cont[10].ACLR
iRST => Frame_Cont[11].ACLR
iRST => Frame_Cont[12].ACLR
iRST => Frame_Cont[13].ACLR
iRST => Frame_Cont[14].ACLR
iRST => Frame_Cont[15].ACLR
iRST => Frame_Cont[16].ACLR
iRST => Frame_Cont[17].ACLR
iRST => Frame_Cont[18].ACLR
iRST => Frame_Cont[19].ACLR
iRST => Frame_Cont[20].ACLR
iRST => Frame_Cont[21].ACLR
iRST => Frame_Cont[22].ACLR
iRST => Frame_Cont[23].ACLR
iRST => Frame_Cont[24].ACLR
iRST => Frame_Cont[25].ACLR
iRST => Frame_Cont[26].ACLR
iRST => Frame_Cont[27].ACLR
iRST => Frame_Cont[28].ACLR
iRST => Frame_Cont[29].ACLR
iRST => Frame_Cont[30].ACLR
iRST => Frame_Cont[31].ACLR
iRST => Pre_FVAL.ACLR
iRST => mCCD_FVAL.ACLR
iRST => mCCD_LVAL.ACLR
iRST => mCCD_DATA[9].ACLR
iRST => mCCD_DATA[8].ACLR
iRST => mCCD_DATA[7].ACLR
iRST => mCCD_DATA[6].ACLR
iRST => mCCD_DATA[5].ACLR
iRST => mCCD_DATA[4].ACLR
iRST => mCCD_DATA[3].ACLR
iRST => mCCD_DATA[2].ACLR
iRST => mCCD_DATA[1].ACLR
iRST => mCCD_DATA[0].ACLR
iRST => X_Cont[10].ACLR
iRST => X_Cont[9].ACLR
iRST => X_Cont[8].ACLR
iRST => X_Cont[7].ACLR
iRST => X_Cont[6].ACLR
iRST => X_Cont[5].ACLR
iRST => X_Cont[4].ACLR
iRST => X_Cont[3].ACLR
iRST => X_Cont[2].ACLR
iRST => X_Cont[1].ACLR
iRST => X_Cont[0].ACLR
iRST => Y_Cont[10].ACLR
iRST => Y_Cont[9].ACLR
iRST => Y_Cont[8].ACLR
iRST => Y_Cont[7].ACLR
iRST => Y_Cont[6].ACLR
iRST => Y_Cont[5].ACLR
iRST => Y_Cont[4].ACLR
iRST => Y_Cont[3].ACLR
iRST => Y_Cont[2].ACLR
iRST => Y_Cont[1].ACLR
iRST => Y_Cont[0].ACLR


|DE2_CCD_PIP|RAW2RGB_2X:u4
oRed[0] <= mCCD_R[0].DB_MAX_OUTPUT_PORT_TYPE
oRed[1] <= mCCD_R[1].DB_MAX_OUTPUT_PORT_TYPE
oRed[2] <= mCCD_R[2].DB_MAX_OUTPUT_PORT_TYPE
oRed[3] <= mCCD_R[3].DB_MAX_OUTPUT_PORT_TYPE
oRed[4] <= mCCD_R[4].DB_MAX_OUTPUT_PORT_TYPE
oRed[5] <= mCCD_R[5].DB_MAX_OUTPUT_PORT_TYPE
oRed[6] <= mCCD_R[6].DB_MAX_OUTPUT_PORT_TYPE
oRed[7] <= mCCD_R[7].DB_MAX_OUTPUT_PORT_TYPE
oRed[8] <= mCCD_R[8].DB_MAX_OUTPUT_PORT_TYPE
oRed[9] <= mCCD_R[9].DB_MAX_OUTPUT_PORT_TYPE
oGreen[0] <= mCCD_G[1].DB_MAX_OUTPUT_PORT_TYPE
oGreen[1] <= mCCD_G[2].DB_MAX_OUTPUT_PORT_TYPE
oGreen[2] <= mCCD_G[3].DB_MAX_OUTPUT_PORT_TYPE
oGreen[3] <= mCCD_G[4].DB_MAX_OUTPUT_PORT_TYPE
oGreen[4] <= mCCD_G[5].DB_MAX_OUTPUT_PORT_TYPE
oGreen[5] <= mCCD_G[6].DB_MAX_OUTPUT_PORT_TYPE
oGreen[6] <= mCCD_G[7].DB_MAX_OUTPUT_PORT_TYPE
oGreen[7] <= mCCD_G[8].DB_MAX_OUTPUT_PORT_TYPE
oGreen[8] <= mCCD_G[9].DB_MAX_OUTPUT_PORT_TYPE
oGreen[9] <= mCCD_G[10].DB_MAX_OUTPUT_PORT_TYPE
oBlue[0] <= mCCD_B[0].DB_MAX_OUTPUT_PORT_TYPE
oBlue[1] <= mCCD_B[1].DB_MAX_OUTPUT_PORT_TYPE
oBlue[2] <= mCCD_B[2].DB_MAX_OUTPUT_PORT_TYPE
oBlue[3] <= mCCD_B[3].DB_MAX_OUTPUT_PORT_TYPE
oBlue[4] <= mCCD_B[4].DB_MAX_OUTPUT_PORT_TYPE
oBlue[5] <= mCCD_B[5].DB_MAX_OUTPUT_PORT_TYPE
oBlue[6] <= mCCD_B[6].DB_MAX_OUTPUT_PORT_TYPE
oBlue[7] <= mCCD_B[7].DB_MAX_OUTPUT_PORT_TYPE
oBlue[8] <= mCCD_B[8].DB_MAX_OUTPUT_PORT_TYPE
oBlue[9] <= mCCD_B[9].DB_MAX_OUTPUT_PORT_TYPE
oDVAL <= mDVAL.DB_MAX_OUTPUT_PORT_TYPE
iX_Cont[0] => mDVAL~0.IN0
iX_Cont[0] => Equal0.IN0
iX_Cont[0] => Equal1.IN0
iX_Cont[0] => Equal2.IN0
iX_Cont[0] => Equal3.IN1
iX_Cont[1] => ~NO_FANOUT~
iX_Cont[2] => ~NO_FANOUT~
iX_Cont[3] => ~NO_FANOUT~
iX_Cont[4] => ~NO_FANOUT~
iX_Cont[5] => ~NO_FANOUT~
iX_Cont[6] => ~NO_FANOUT~
iX_Cont[7] => ~NO_FANOUT~
iX_Cont[8] => ~NO_FANOUT~
iX_Cont[9] => ~NO_FANOUT~
iX_Cont[10] => ~NO_FANOUT~
iY_Cont[0] => mDVAL~0.IN1
iY_Cont[0] => Equal0.IN1
iY_Cont[0] => Equal1.IN1
iY_Cont[0] => Equal2.IN1
iY_Cont[0] => Equal3.IN0
iY_Cont[1] => ~NO_FANOUT~
iY_Cont[2] => ~NO_FANOUT~
iY_Cont[3] => ~NO_FANOUT~
iY_Cont[4] => ~NO_FANOUT~
iY_Cont[5] => ~NO_FANOUT~
iY_Cont[6] => ~NO_FANOUT~
iY_Cont[7] => ~NO_FANOUT~
iY_Cont[8] => ~NO_FANOUT~
iY_Cont[9] => ~NO_FANOUT~
iY_Cont[10] => ~NO_FANOUT~
iDATA[0] => iDATA[0]~9.IN1
iDATA[1] => iDATA[1]~8.IN1
iDATA[2] => iDATA[2]~7.IN1
iDATA[3] => iDATA[3]~6.IN1
iDATA[4] => iDATA[4]~5.IN1
iDATA[5] => iDATA[5]~4.IN1
iDATA[6] => iDATA[6]~3.IN1
iDATA[7] => iDATA[7]~2.IN1
iDATA[8] => iDATA[8]~1.IN1
iDATA[9] => iDATA[9]~0.IN1
iDVAL => iDVAL~0.IN1
iCLK => iCLK~0.IN1
iRST => mCCD_R[9].ACLR
iRST => mCCD_R[8].ACLR
iRST => mCCD_R[7].ACLR
iRST => mCCD_R[6].ACLR
iRST => mCCD_R[5].ACLR
iRST => mCCD_R[4].ACLR
iRST => mCCD_R[3].ACLR
iRST => mCCD_R[2].ACLR
iRST => mCCD_R[1].ACLR
iRST => mCCD_R[0].ACLR
iRST => mCCD_G[10].ACLR
iRST => mCCD_G[9].ACLR
iRST => mCCD_G[8].ACLR
iRST => mCCD_G[7].ACLR
iRST => mCCD_G[6].ACLR
iRST => mCCD_G[5].ACLR
iRST => mCCD_G[4].ACLR
iRST => mCCD_G[3].ACLR
iRST => mCCD_G[2].ACLR
iRST => mCCD_G[1].ACLR
iRST => mCCD_B[9].ACLR
iRST => mCCD_B[8].ACLR
iRST => mCCD_B[7].ACLR
iRST => mCCD_B[6].ACLR
iRST => mCCD_B[5].ACLR
iRST => mCCD_B[4].ACLR
iRST => mCCD_B[3].ACLR
iRST => mCCD_B[2].ACLR
iRST => mCCD_B[1].ACLR
iRST => mCCD_B[0].ACLR
iRST => mDATAd_0[9].ACLR
iRST => mDATAd_0[8].ACLR
iRST => mDATAd_0[7].ACLR
iRST => mDATAd_0[6].ACLR
iRST => mDATAd_0[5].ACLR
iRST => mDATAd_0[4].ACLR
iRST => mDATAd_0[3].ACLR
iRST => mDATAd_0[2].ACLR
iRST => mDATAd_0[1].ACLR
iRST => mDATAd_0[0].ACLR
iRST => mDATAd_1[9].ACLR
iRST => mDATAd_1[8].ACLR
iRST => mDATAd_1[7].ACLR
iRST => mDATAd_1[6].ACLR
iRST => mDATAd_1[5].ACLR
iRST => mDATAd_1[4].ACLR
iRST => mDATAd_1[3].ACLR
iRST => mDATAd_1[2].ACLR
iRST => mDATAd_1[1].ACLR
iRST => mDATAd_1[0].ACLR
iRST => mDVAL.ACLR


|DE2_CCD_PIP|RAW2RGB_2X:u4|Line_Buffer:u0
clken => clken~0.IN1
clock => clock~0.IN1
shiftin[0] => shiftin[0]~9.IN1
shiftin[1] => shiftin[1]~8.IN1
shiftin[2] => shiftin[2]~7.IN1
shiftin[3] => shiftin[3]~6.IN1
shiftin[4] => shiftin[4]~5.IN1
shiftin[5] => shiftin[5]~4.IN1
shiftin[6] => shiftin[6]~3.IN1
shiftin[7] => shiftin[7]~2.IN1
shiftin[8] => shiftin[8]~1.IN1
shiftin[9] => shiftin[9]~0.IN1
shiftout[0] <= altshift_taps:altshift_taps_component.shiftout
shiftout[1] <= altshift_taps:altshift_taps_component.shiftout
shiftout[2] <= altshift_taps:altshift_taps_component.shiftout
shiftout[3] <= altshift_taps:altshift_taps_component.shiftout
shiftout[4] <= altshift_taps:altshift_taps_component.shiftout
shiftout[5] <= altshift_taps:altshift_taps_component.shiftout
shiftout[6] <= altshift_taps:altshift_taps_component.shiftout
shiftout[7] <= altshift_taps:altshift_taps_component.shiftout
shiftout[8] <= altshift_taps:altshift_taps_component.shiftout
shiftout[9] <= altshift_taps:altshift_taps_component.shiftout
taps0x[0] <= altshift_taps:altshift_taps_component.taps
taps0x[1] <= altshift_taps:altshift_taps_component.taps
taps0x[2] <= altshift_taps:altshift_taps_component.taps
taps0x[3] <= altshift_taps:altshift_taps_component.taps
taps0x[4] <= altshift_taps:altshift_taps_component.taps
taps0x[5] <= altshift_taps:altshift_taps_component.taps
taps0x[6] <= altshift_taps:altshift_taps_component.taps
taps0x[7] <= altshift_taps:altshift_taps_component.taps
taps0x[8] <= altshift_taps:altshift_taps_component.taps
taps0x[9] <= altshift_taps:altshift_taps_component.taps
taps1x[0] <= altshift_taps:altshift_taps_component.taps
taps1x[1] <= altshift_taps:altshift_taps_component.taps
taps1x[2] <= altshift_taps:altshift_taps_component.taps
taps1x[3] <= altshift_taps:altshift_taps_component.taps
taps1x[4] <= altshift_taps:altshift_taps_component.taps
taps1x[5] <= altshift_taps:altshift_taps_component.taps
taps1x[6] <= altshift_taps:altshift_taps_component.taps
taps1x[7] <= altshift_taps:altshift_taps_component.taps
taps1x[8] <= altshift_taps:altshift_taps_component.taps
taps1x[9] <= altshift_taps:altshift_taps_component.taps


|DE2_CCD_PIP|RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
shiftin[0] => shift_taps_gkn:auto_generated.shiftin[0]
shiftin[1] => shift_taps_gkn:auto_generated.shiftin[1]
shiftin[2] => shift_taps_gkn:auto_generated.shiftin[2]
shiftin[3] => shift_taps_gkn:auto_generated.shiftin[3]
shiftin[4] => shift_taps_gkn:auto_generated.shiftin[4]
shiftin[5] => shift_taps_gkn:auto_generated.shiftin[5]
shiftin[6] => shift_taps_gkn:auto_generated.shiftin[6]
shiftin[7] => shift_taps_gkn:auto_generated.shiftin[7]
shiftin[8] => shift_taps_gkn:auto_generated.shiftin[8]
shiftin[9] => shift_taps_gkn:auto_generated.shiftin[9]
clock => shift_taps_gkn:auto_generated.clock
clken => shift_taps_gkn:auto_generated.clken
shiftout[0] <= shift_taps_gkn:auto_generated.shiftout[0]
shiftout[1] <= shift_taps_gkn:auto_generated.shiftout[1]
shiftout[2] <= shift_taps_gkn:auto_generated.shiftout[2]
shiftout[3] <= shift_taps_gkn:auto_generated.shiftout[3]
shiftout[4] <= shift_taps_gkn:auto_generated.shiftout[4]
shiftout[5] <= shift_taps_gkn:auto_generated.shiftout[5]
shiftout[6] <= shift_taps_gkn:auto_generated.shiftout[6]
shiftout[7] <= shift_taps_gkn:auto_generated.shiftout[7]
shiftout[8] <= shift_taps_gkn:auto_generated.shiftout[8]
shiftout[9] <= shift_taps_gkn:auto_generated.shiftout[9]
taps[0] <= shift_taps_gkn:auto_generated.taps[0]
taps[1] <= shift_taps_gkn:auto_generated.taps[1]
taps[2] <= shift_taps_gkn:auto_generated.taps[2]
taps[3] <= shift_taps_gkn:auto_generated.taps[3]
taps[4] <= shift_taps_gkn:auto_generated.taps[4]
taps[5] <= shift_taps_gkn:auto_generated.taps[5]
taps[6] <= shift_taps_gkn:auto_generated.taps[6]
taps[7] <= shift_taps_gkn:auto_generated.taps[7]
taps[8] <= shift_taps_gkn:auto_generated.taps[8]
taps[9] <= shift_taps_gkn:auto_generated.taps[9]
taps[10] <= shift_taps_gkn:auto_generated.taps[10]
taps[11] <= shift_taps_gkn:auto_generated.taps[11]
taps[12] <= shift_taps_gkn:auto_generated.taps[12]
taps[13] <= shift_taps_gkn:auto_generated.taps[13]
taps[14] <= shift_taps_gkn:auto_generated.taps[14]
taps[15] <= shift_taps_gkn:auto_generated.taps[15]
taps[16] <= shift_taps_gkn:auto_generated.taps[16]
taps[17] <= shift_taps_gkn:auto_generated.taps[17]
taps[18] <= shift_taps_gkn:auto_generated.taps[18]
taps[19] <= shift_taps_gkn:auto_generated.taps[19]


|DE2_CCD_PIP|RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated
clken => altsyncram_4m81:altsyncram2.clocken0
clken => cntr_3rf:cntr1.clk_en
clock => altsyncram_4m81:altsyncram2.clock0
clock => cntr_3rf:cntr1.clock
shiftin[0] => altsyncram_4m81:altsyncram2.data_a[0]
shiftin[1] => altsyncram_4m81:altsyncram2.data_a[1]
shiftin[2] => altsyncram_4m81:altsyncram2.data_a[2]
shiftin[3] => altsyncram_4m81:altsyncram2.data_a[3]
shiftin[4] => altsyncram_4m81:altsyncram2.data_a[4]
shiftin[5] => altsyncram_4m81:altsyncram2.data_a[5]
shiftin[6] => altsyncram_4m81:altsyncram2.data_a[6]
shiftin[7] => altsyncram_4m81:altsyncram2.data_a[7]
shiftin[8] => altsyncram_4m81:altsyncram2.data_a[8]
shiftin[9] => altsyncram_4m81:altsyncram2.data_a[9]
shiftout[0] <= altsyncram_4m81:altsyncram2.q_b[10]
shiftout[1] <= altsyncram_4m81:altsyncram2.q_b[11]
shiftout[2] <= altsyncram_4m81:altsyncram2.q_b[12]
shiftout[3] <= altsyncram_4m81:altsyncram2.q_b[13]
shiftout[4] <= altsyncram_4m81:altsyncram2.q_b[14]
shiftout[5] <= altsyncram_4m81:altsyncram2.q_b[15]
shiftout[6] <= altsyncram_4m81:altsyncram2.q_b[16]
shiftout[7] <= altsyncram_4m81:altsyncram2.q_b[17]
shiftout[8] <= altsyncram_4m81:altsyncram2.q_b[18]
shiftout[9] <= altsyncram_4m81:altsyncram2.q_b[19]
taps[0] <= altsyncram_4m81:altsyncram2.q_b[0]
taps[1] <= altsyncram_4m81:altsyncram2.q_b[1]
taps[2] <= altsyncram_4m81:altsyncram2.q_b[2]
taps[3] <= altsyncram_4m81:altsyncram2.q_b[3]
taps[4] <= altsyncram_4m81:altsyncram2.q_b[4]
taps[5] <= altsyncram_4m81:altsyncram2.q_b[5]
taps[6] <= altsyncram_4m81:altsyncram2.q_b[6]
taps[7] <= altsyncram_4m81:altsyncram2.q_b[7]
taps[8] <= altsyncram_4m81:altsyncram2.q_b[8]
taps[9] <= altsyncram_4m81:altsyncram2.q_b[9]
taps[10] <= altsyncram_4m81:altsyncram2.q_b[10]
taps[11] <= altsyncram_4m81:altsyncram2.q_b[11]
taps[12] <= altsyncram_4m81:altsyncram2.q_b[12]
taps[13] <= altsyncram_4m81:altsyncram2.q_b[13]
taps[14] <= altsyncram_4m81:altsyncram2.q_b[14]
taps[15] <= altsyncram_4m81:altsyncram2.q_b[15]
taps[16] <= altsyncram_4m81:altsyncram2.q_b[16]
taps[17] <= altsyncram_4m81:altsyncram2.q_b[17]
taps[18] <= altsyncram_4m81:altsyncram2.q_b[18]
taps[19] <= altsyncram_4m81:altsyncram2.q_b[19]


|DE2_CCD_PIP|RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated|altsyncram_4m81:altsyncram2
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR